Patents by Inventor Shuichi Miyaoka
Shuichi Miyaoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110049988Abstract: The present invention aims to provide a control system which is capable of building high-precision current detecting means in a single-chip LSI and can be realized at a lower cost, and a semiconductor device used in the control system. Drive circuits are provided inside the same semiconductor chip. The drive circuits are equipped with: current detecting shunt resistors each of which is provided in each of the drive circuits and detects a current flowing through a load, the current detecting shunt resistors being provided within a semiconductor chip by the same process; a dummy resistor provided within the semiconductor chip by the same process as the current detecting shunt resistors; and a calibration reference externally attached to the semiconductor chip and connected to the dummy resistor. A correcting means corrects the values of currents that flow through the current detecting shunt resistors, using the dummy resistor and the calibration reference.Type: ApplicationFiled: August 12, 2010Publication date: March 3, 2011Applicant: Hitachi Automotive Systems, Ltd.Inventors: Nobuyasu KANEKAWA, Teppei HIROTSU, Itaru TANABE, Shuichi MIYAOKA, Ryoichi OURA
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Patent number: 7162671Abstract: Inputs of a control circuit are connected to a terminal to which an external operation control signal is supplied and a terminal to which a timing signal used exclusively for testing is supplied, and the control circuit is made controllable such that, in a test mode, a state of an internal operation control signal is changed in response to a change of a state of the external operation control signal, and the internal operation control signal is changed in response to the timing exclusively used for testing, whereas, in a normal operation mode, the state of the internal operation control signal is changed in response to the change of the state of the external operation control signal, and the internal operation control signal is changed in response to the change of the external operation control signal.Type: GrantFiled: August 16, 2004Date of Patent: January 9, 2007Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co. Ltd.Inventors: Masatoshi Hasegawa, Shuichi Miyaoka, Hiroshi Akasaki, Masahiro Katayama
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Patent number: 7113434Abstract: In a semiconductor integrated circuit device that includes macro cells (circuit blocks that can be designed independently) such as a storage circuit and operates synchronously with an external clock, total delay time from signal input to output is reduced and the speed of operation is increased. In the semiconductor integrated circuit device which has plural circuit blocks coupled in series for signal transmission and whose whole operation is controlled by a clock signal, the semiconductor integrated circuit device including first circuit blocks that receive input signals in response to a first timing signal based on a clock signal, and a second circuit block that forms output signals in response to a second timing signal based on the clock signal, a time difference between the first timing signal and the second timing signal is set to a non-integral multiple of the cycle of the clock signal.Type: GrantFiled: April 14, 2004Date of Patent: September 26, 2006Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Hiroshi Akasaki, Shuichi Miyaoka, Yuji Yokoyama, Masatoshi Hasegawa, Kozaburo Kurita
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Patent number: 7023749Abstract: The present invention provides a semiconductor integrated circuit device equipped with a memory circuit, which realizes speeding up of its operation in a simple configuration or realizes high reliability and enhancement of product yields in a simple configuration. A memory cell is selected from within a memory array having a plurality of memory cells by a selector or selection circuit. MOSFETs constituting a precharge circuit provided for signal lines for transferring a read signal therefrom to a main amplifier are respectively brought to an on state based on a memory cell select start signal transferred to the selection circuit and brought to an off state prior to the transfer of the read signal from the memory cell to thereby complete precharging, whereby NBTI degradation at standby is avoided.Type: GrantFiled: January 24, 2005Date of Patent: April 4, 2006Assignee: Hitachi, Ltd.Inventors: Masatoshi Hasegawa, Shuichi Miyaoka
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Publication number: 20050162969Abstract: The present invention provides a semiconductor integrated circuit device equipped with a memory circuit, which realizes speeding up of its operation in a simple configuration or realizes high reliability and enhancement of product yields in a simple configuration. A memory cell is selected from within a memory array having a plurality of memory cells by a selector or selection circuit. MOSFETs constituting a precharge circuit provided for signal lines for transferring a read signal therefrom to a main amplifier are respectively brought to an on state based on a memory cell select start signal transferred to the selection circuit and brought to an off state prior to the transfer of the read signal from the memory cell to thereby complete precharging, whereby NBTI degradation at standby is avoided.Type: ApplicationFiled: January 24, 2005Publication date: July 28, 2005Inventors: Masatoshi Hasegawa, Shuichi Miyaoka
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Patent number: 6865127Abstract: The present invention provides a semiconductor integrated circuit device equipped with a memory circuit, which realizes speeding up of its operation in a simple configuration or realizes high reliability and enhancement of product yields in a simple configuration. A memory cell is selected from within a memory array having a plurality of memory cells by a selector or selection circuit. MOSFETs constituting a precharge circuit provided for signal lines for transferring a read signal therefrom to a main amplifier are respectively brought to an on state based on a memory cell select start signal transferred to the selection circuit and brought to an off state prior to the transfer of the read signal from the memory cell to thereby complete precharging, whereby NBTI degradation at standby is avoided.Type: GrantFiled: April 14, 2003Date of Patent: March 8, 2005Assignee: Hitachi, Ltd.Inventors: Masatoshi Hasegawa, Shuichi Miyaoka
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Publication number: 20050018461Abstract: Inputs of a control circuit are connected to a terminal to which an external operation control signal is supplied and a terminal to which a timing signal used exclusively for testing is supplied, and the control circuit is made controllable such that, in a test mode, a state of an internal operation control signal is changed in response to a change of a state of the external operation control signal, and the internal operation control signal is changed in response to the timing exclusively used for testing, whereas, in a normal operation mode, the state of the internal operation control signal is changed in response to the change of the state of the external operation control signal, and the internal operation control signal is changed in response to the change of the external operation control signal.Type: ApplicationFiled: August 16, 2004Publication date: January 27, 2005Inventors: Masatoshi Hasegawa, Shuichi Miyaoka, Hiroshi Akasaki, Masahiro Katayama
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Publication number: 20040196080Abstract: In a semiconductor integrated circuit device that includes macro cells (circuit blocks that can be designed independently) such as a storage circuit and operates synchronously with an external clock, total delay time from signal input to output is reduced and the speed of operation is increased. In the semiconductor integrated circuit device which has plural circuit blocks coupled in series for signal transmission and whose whole operation is controlled by a clock signal, the semiconductor integrated circuit device including first circuit blocks that receive input signals in response to a first timing signal based on a clock signal, and a second circuit block that forms output signals in response to a second timing signal based on the clock signal, a time difference between the first timing signal and the second timing signal is set to a non-integral multiple of the cycle of the clock signal.Type: ApplicationFiled: April 14, 2004Publication date: October 7, 2004Applicants: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Hiroshi Akasaki, Shuichi Miyaoka, Yuji Yokoyama, Masatoshi Hasegawa, Kozaburo Kurita
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Patent number: 6794678Abstract: Inputs of a control circuit are connected to a terminal to which an external operation control signal is supplied and a terminal to which a timing signal used exclusively for testing is supplied, and the control circuit is made controllable such that, in a test mode, a state of an internal operation control signal is changed in response to a change of a state of the external operation control signal, and the internal operation control signal is changed in response to the timing exclusively used for testing, whereas, in a normal operation mode, the state of the internal operation control signal is changed in response to the change of the state of the external operation control signal, and the internal operation control signal is changed in response to the change of the external operation control signal.Type: GrantFiled: January 30, 2002Date of Patent: September 21, 2004Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Masatoshi Hasegawa, Shuichi Miyaoka, Hiroshi Akasaki, Masahiro Katayama
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Patent number: 6735129Abstract: In a semiconductor integrated circuit device that includes macro cells (circuit blocks that can be designed independently) such as a storage circuit and operates synchronously with an external clock, total delay time from signal input to output is reduced and the speed of operation is increased. In the semiconductor integrated circuit device which has plural circuit blocks coupled in series for signal transmission and whose whole operation is controlled by a clock signal, the semiconductor integrated circuit device including first circuit blocks that receive input signals in response to a first timing signal based on a clock signal, and a second circuit block that forms output signals in response to a second timing signal based on the clock signal, a time difference between the first timing signal and the second timing signal is set to a non-integral multiple of the cycle of the clock signal.Type: GrantFiled: May 24, 2002Date of Patent: May 11, 2004Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Hiroshi Akasaki, Shuichi Miyaoka, Yuji Yokoyama, Masatoshi Hasegawa, Kozaburo Kurita
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Patent number: 6714477Abstract: Read buffers (RB0-RB3) are capable of holding data read out from a plurality of memory blocks (BNK0-BNK7) that are capable of parallel operation in response to a state in which the read data cannot be externally outputted from an external interface means; and, selection means (40, 41, 42) are provided for selecting data read out from one of the memory blocks, or data read out from one of the read buffers, and for feeding it to the external interface means, while the external-output-incapable state is not present. In this way, when there is a possibility that an output of read data will cause a resource competition, this read data is stored in a read buffer, and when there is no such possibility, then the read data can be externally outputted directly, thereby improving the throughput of read data output operations.Type: GrantFiled: July 3, 2002Date of Patent: March 30, 2004Assignee: Hitachi, Ltd.Inventors: Michiaki Nakayama, Hideki Sakakibara, Toru Kobayashi, Shuichi Miyaoka, Yuji Yokoyama, Hideo Sawamoto, Masaji Kume
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Publication number: 20030198110Abstract: The present invention provides a semiconductor integrated circuit device equipped with a memory circuit, which realizes speeding up of its operation in a simple configuration or realizes high reliability and enhancement of product yields in a simple configuration. A memory cell is selected from within a memory array having a plurality of memory cells by a selector or selection circuit. MOSFETs constituting a precharge circuit provided for signal lines for transferring a read signal therefrom to a main amplifier are respectively brought to an on state based on a memory cell select start signal transferred to the selection circuit and brought to an off state prior to the transfer of the read signal from the memory cell to thereby complete precharging, whereby NBTI degradation at standby is avoided.Type: ApplicationFiled: April 14, 2003Publication date: October 23, 2003Applicant: Hitachi, Ltd.Inventors: Masatoshi Hasegawa, Shuichi Miyaoka
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Patent number: 6570800Abstract: The column address strobe signal (CAS) which is changed in cycles as many as a plurality of times that of a clock signal cycle is input to the memory block (MBK0 to MBKn). A plurality of serial data readout from the memory cell array (10) and parallel/serial converted by a parallel/serial converter circuit (21) in synchronism with a clock signal cycle are output for every cycle when the column address signal (CASADR) is changed. Parallel data input to the memory block and serial/parallel converted by a serial/parallel converter circuit (25) in synchronism with the clock signal cycle are written in the memory cell array. In this way, the access specification that the column address strobe signal is varied once per n cycles of the clock signal allows for a more rapid memory operation.Type: GrantFiled: January 10, 2001Date of Patent: May 27, 2003Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Yousuke Tanaka, Masahiro Katayama, Yuji Yokoyama, Hiroshi Akasaki, Shuichi Miyaoka, Toru Kobayashi
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Publication number: 20020176292Abstract: In a semiconductor integrated circuit device that includes macro cells (circuit blocks that can be designed independently) such as a storage circuit and operates synchronously with an external clock, total delay time from signal input to output is reduced and the speed of operation is increased. In the semiconductor integrated circuit device which has plural circuit blocks coupled in series for signal transmission and whose whole operation is controlled by a clock signal, the semiconductor integrated circuit device including first circuit blocks that receive input signals in response to a first timing signal based on a clock signal, and a second circuit block that forms output signals in response to a second timing signal based on the clock signal, a time difference between the first timing signal and the second timing signal is set to a non-integral multiple of the cycle of the clock signal.Type: ApplicationFiled: May 24, 2002Publication date: November 28, 2002Applicant: Hitachi, Ltd.Inventors: Hiroshi Akasaki, Shuichi Miyaoka, Yuji Yokoyama, Masatoshi Hasegawa, Kozaburo Kurita
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Publication number: 20020176308Abstract: Read buffers (RB0-RB3) are capable of holding data read out from a plurality of memory blocks (BNK0-BNK7) that are capable of parallel operation in response to a state in which the read data cannot be externally outputted from an external interface means; and, selection means (40, 41, 42) are provided for selecting data read out from one of the memory blocks, or data read out from one of the read buffers, and for feeding it to the external interface means, while the external-output-incapable state is not present. In this way, when there is a possibility that an output of read data will cause a resource competition, this read data is stored in a read buffer, and when there is no such possibility, then the read data can be externally outputted directly, thereby improving the throughput of read data output operations.Type: ApplicationFiled: July 3, 2002Publication date: November 28, 2002Inventors: Michiaki Nakayama, Hideki Sakakibara, Toru Kobayashi, Shuichi Miyaoka, Yuji Yokoyama, Hideo Sawamoto, Masaji Kume
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Publication number: 20020118018Abstract: Inputs of a control circuit are connected to a terminal to which an external operation control signal is supplied and a terminal to which a timing signal used exclusively for testing is supplied, and the control circuit is made controllable such that, in a test mode, a state of an internal operation control signal is changed in response to a change of a state of the external operation control signal, and the internal operation control signal is changed in response to the timing exclusively used for testing, whereas, in a normal operation mode, the state of the internal operation control signal is changed in response to the change of the state of the external operation control signal, and the internal operation control signal is changed in response to the change of the external operation control signal.Type: ApplicationFiled: January 30, 2002Publication date: August 29, 2002Inventors: Masatoshi Hasegawa, Shuichi Miyaoka, Hiroshi Akasaki, Masahiro Katayama
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Patent number: 6430103Abstract: Read buffers (RB0-RB3) are capable of holding data read out from a plurality of memory blocks (BNK0-BNK7) that are capable of parallel operation in response to a state in which the read data cannot be externally outputted from an external interface means; and, selection means (40, 41, 42) are provided for selecting data read out from one of the memory blocks, or data read out from one of the read buffers, and for feeding it to the external interface means, while the external-output-incapable state is not present. In this way, when there is a possibility that an output of read data will cause a resource competition, this read data is stored in a read buffer, and when there is no such possibility, then the read data can be externally outputted directly, thereby improving the throughput of read data output operations.Type: GrantFiled: February 5, 2001Date of Patent: August 6, 2002Assignee: Hitachi, Ltd.Inventors: Michiaki Nakayama, Hideki Sakakibara, Toru Kobayashi, Shuichi Miyaoka, Yuji Yokoyama, Hideo Sawamoto, Masaji Kume
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Publication number: 20010012232Abstract: The throughput of external output actions of read data from memory blocks that are capable of parallel operation is improved.Type: ApplicationFiled: February 5, 2001Publication date: August 9, 2001Inventors: Michiaki Nakayama, Hideki Sakakibara, Toru Kobayashi, Shuichi Miyaoka, Yuji Yokoyama, Hideo Sawamoto, Masaji Kume
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Publication number: 20010007539Abstract: The column address strobe signal (CAS) which is changed in cycles as many as a plurality of times of a clock signal cycle is input to the memory block (MBK0 to MBKn). A plurality of serial data readout from the memory cell array (10) and parallel/serial converted by a parallel/serial converter circuit (21) in synchronous with a clock signal cycle are output for every cycle when the column address signal (CASADR) is changed. Parallel data input to the memory block and serial/parallel converted by a serial/parallel converter circuit (25) in synchronous with the clock signal cycle are written in the memory cell array. In this way, the access specification that the column address strobe signal is varied once per n cycles of the clock signal allows more rapid memory operation.Type: ApplicationFiled: January 10, 2001Publication date: July 12, 2001Inventors: Yousuke Tanaka, Masahiro Katayama, Yuji Yokoyama, Hiroshi Akasaki, Shuichi Miyaoka, Toru Kobayashi
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Patent number: 6191990Abstract: A semiconductor integrated circuit device has a memory array which includes amplifying MOSFETs of sense amplifiers which amplify small voltages read out of dynamic memory cells onto bit lines and column switch MOSFETs which select bit lines, a read/write section which includes main amplifiers for reading out stored data from memory cells selected by the column switch, and a logic circuit which implements the input/output operation of data with the read/write section. Two capacitors each having a first electrode which corresponds to a plate electrode with the same structure as that of storage capacitors of dynamic memory cells and a second electrode which is multiple commonly-connected storage nodes of the storage capacitors are arranged in serial connection, disposed contiguously to the read/write section, and connected between operation voltage lines of the read/write section.Type: GrantFiled: February 22, 2000Date of Patent: February 20, 2001Assignee: Hitachi, Ltd.Inventors: Nobutaka Itoh, Shuichi Miyaoka, Yuji Yokoyama, Michiaki Nakayama, Mitsugu Kusunoki, Kazumasa Takashima, Hideki Sakakibara, Toru Kobayashi