Patents by Inventor Shuichi Murai

Shuichi Murai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11936377
    Abstract: Apparatuses including an impedance code selector are disclosed. An example apparatus according to the disclosure includes an impedance calibration circuit, an impedance code selector and a driver circuit in a data input/output circuit. The impedance calibration circuit provides a first impedance code. The impedance code selector provides either the first impedance code or a second impedance code. The driver circuit receives either the first impedance code or the second impedance code from the impedance code selector.
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: March 19, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Shuichi Murai, Nobuki Takahashi
  • Publication number: 20230370065
    Abstract: Apparatuses including an impedance code selector are disclosed. An example apparatus according to the disclosure includes an impedance calibration circuit, an impedance code selector and a driver circuit in a data input/output circuit. The impedance calibration circuit provides a first impedance code. The impedance code selector provides either the first impedance code or a second impedance code. The driver circuit receives either the first impedance code or the second impedance code from the impedance code selector.
    Type: Application
    Filed: May 10, 2022
    Publication date: November 16, 2023
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: SHUICHI MURAI, NOBUKI TAKAHASHI
  • Patent number: 10734046
    Abstract: Apparatuses and methods for providing voltages to conductive lines between which clock signal lines are disposed are disclosed. Voltages provided to the conductive lines may provide voltage conditions for clock signals on the clock signal lines that are relatively the same for at least some of the clock edges of the clock signals. Having the same voltage conditions may mitigate variations in timing/phase between the clock signals due to different voltage influences when a clock signal transitions from a low clock level to a high clock level.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: August 4, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Katsuhiro Kitagawa, Akira Yamashita, Shuichi Murai, Kohei Nakamura
  • Patent number: 10693460
    Abstract: Memory devices employ circuitry that may be used to adjust the output impedance. Embodiments describe herein relate to fuse-based adjustment circuitry that may be used to assist output impedance compensation such as ZQ calibration, and facilitate reduction in the dimensions and/or power consumption of the memory device.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: June 23, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Hiroki Takahashi, Shuichi Murai
  • Publication number: 20200118608
    Abstract: Apparatuses and methods for providing voltages to conductive lines between which clock signal lines are disposed are disclosed. Voltages provided to the conductive lines may provide voltage conditions for clock signals on the clock signal lines that are relatively the same for at least some of the clock edges of the clock signals. Having the same voltage conditions may mitigate variations in timing/phase between the clock signals due to different voltage influences when a clock signal transitions from a low clock level to a high clock level.
    Type: Application
    Filed: June 10, 2019
    Publication date: April 16, 2020
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Katsuhiro Kitagawa, Akira Yamashita, Shuichi Murai, Kohei Nakamura
  • Patent number: 10418081
    Abstract: Apparatuses and methods for providing voltages to conductive lines between which clock signal lines are disposed are disclosed. Voltages provided to the conductive lines may provide voltage conditions for clock signals on the clock signal lines that are relatively the same for at least some of the clock edges of the clock signals. Having the same voltage conditions may mitigate variations in timing/phase between the clock signals due to different voltage influences when a clock signal transitions from a low clock level to a high clock level.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: September 17, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Katsuhiro Kitagawa, Akira Yamashita, Shuichi Murai, Kohei Nakamura