Abstract: A semiconductor device includes a substrate (e.g., a P-type semiconductor substrate), and an isolation region formed in the substrate to isolate an element formation region from the other region. The semiconductor device also includes a gate electrode formed over the element formation region. The gate electrode extends over each of first and second regions of the isolation region opposing each other with the element formation region interposed therebetween. The semiconductor device further includes a pair of diffusion regions (e.g., N-type diffusion regions) formed in the element formation region so as to be spaced apart from each other in a channel length direction with reference to the gate electrode. At least a portion of each of upper surfaces of the first and second regions is depressed to a depth of not less than 5% of a channel width to be located under an upper surface of the element formation region. In each of resultant depressions also, a portion of the gate electrode is present.

Abstract: A semiconductor device includes a substrate (e.g., a P-type semiconductor substrate), and an isolation region formed in the substrate to isolate an element formation region from the other region. The semiconductor device also includes a gate electrode formed over the element formation region. The gate electrode extends over each of first and second regions of the isolation region opposing each other with the element formation region interposed therebetween. The semiconductor device further includes a pair of diffusion regions (e.g., N-type diffusion regions) formed in the element formation region so as to be spaced apart from each other in a channel length direction with reference to the gate electrode. At least a portion of each of upper surfaces of the first and second regions is depressed to a depth of not less than 5% of a channel width to be located under an upper surface of the element formation region. In each of resultant depressions also, a portion of the gate electrode is present.

Abstract: Disclosed herein is a semiconductor memory device including a plurality of memory cells each includes an active region which is defined in a column direction by a pair of trench isolation regions formed in a semiconductor substrate and in a row direction by an isolation gate conductor lines formed on a first gate insulating film covering the substrate, a source and a drain region selectively formed in the active region to define a channel region of a cell transistor, a second gate insulating film formed on the channel region, a word line formed on the second gate insulating film, a first insulating film covering the active region and the word line, a bit line formed on the first insulating film to overlap with the isolation gate conductor, a bit line connection conductor formed in the first insulating film to connect the drain region to the bit line with being in contact with the sidewall surface of the bit line, a second insulating film covering the bit line and the first insulating film, and a storage capac

Abstract: In a semiconductor device having a first insulator layer on a semiconductor substrate and accumulation electrode layers overlying the first insulator layer, second insulator layers overlie predetermined areas of the first insulator layer and side electrode surfaces of the accumulation electrode layers. Each of the second insulator layers has a primary dielectric constant. A dielectric layer overlies upper surfaces of the accumulation electrode layers and the second insulator layers and has a secondary dielectric constant which is higher than the primary dielectric constant. An opposed electrode layer overlies the dielectric layer.

Abstract: In a semiconductor device having a first insulator layer on a semiconductor substrate and accumulation electrode layers overlying the first insulator layer, second insulator layers overlie predetermined areas of the first insulator layer and side electrode surfaces of the accumulation electrode layers. Each of the second insulator layers has a primary dielectric constant. A dielectric layer overlies upper surfaces of the accumulation electrode layers and the second insulator layers and has a secondary dielectric constant which is higher than the primary dielectric constant. An opposed electrode layer overlies the dielectric layer.

Abstract: A DRAM comprising word lines parallel to an X-axis and bit lines parallel to a Y-axis wherein the memory cell consists of a transistor and a stacked-type charge-storage capacitor is disclosed. The storage node electrode of the stacked-type charge-storage capacitor is formed to project on the surface of the silicon substrate a rectangle of which the major sides are oblique to the X-axis and Y-axis or a pattern consisting of at least two different rectangles. Thereby the perimeter of the storage node electrode becomes more than that in the prior art. This enables the realization of charge-storage capacitors having larger capacitance value than in a conventional DRAM under the same manufacturing conditions. This effect is marked under the conditions where the film thickness of the storage node electrode is more than 1/2 of the minimum feature size, and the distance between two adjacent storage node electrodes is equal to the minimum feature size.

Abstract: A semiconductor memory device is fabricated on a semiconductor substrate and comprises a memory cell array having a plurality of memory cells and located in a predetermined cell area of the semiconductor substrate, a rampart structure formed outside the memory cell array and having an outer wall gently sloping down, an upper insulating layer convering the memory cells and the rampart structure, and at least one wiring layer formed on the upper insulating layer and extending over at least one of the memory cells and the rampart structure, whereby the wiring layer is prevented from non-conformal step coverage and any disconnection.

Abstract: A non-volatile semiconductor memory device includes a gate insulating film which has a relatively thin portion in the vicinity of one of the source and drain regions at which p-n junction breakdown is performed for carrier injection.