Abstract: An information conversion device has one of: a replication necessity analysis unit for specifying where an instruction referred by phi functions is present in one basic block and inserting a transfer instruction therein; an intra-loop constant analysis unit for specifying a closed path in which a phi function reference is circulated and inserting the transfer instruction therein; an inter-instruction dependency analysis unit for specifying where data dependency is present between instructions as a reference destination of the phi functions and inserting the transfer instruction therein; a same instruction reference analysis unit for specifying where the phi functions referring to a result of a same instruction before branching are present and inserting the transfer instruction therein; and a spill out validity analysis unit for storing a value present in a loop processing, loading the value after the loop processing ends, and deleting the transfer instruction.

Abstract: An information processing device is provided that can more flexibly adapt to changes in shape and mounting configuration. The information processing device has a plurality of chips that are integrated in the horizontal direction. A transmission coil and reception coil pair is formed in each of the plurality of chips, and each of the plurality of chips uses horizontal inductive coupling to achieve wireless connection between the chips.

Abstract: A program causes a computer to serve as an information conversion device that is equipped with at least one of (A)-(E): (A) a replication necessity analysis processor specifying a location where an instruction referred to from phi functions present in one basic block is present and inserting an inter-register transfer instruction therein; (B) an intra-loop constant analysis processor specifying a closed path in which the references of the phi functions are circulated and inserting the inter-register transfer instruction therein; (C) an inter-instruction dependency analysis processor specifying a location where data dependency is present between instructions, which are reference destinations of the phi functions, and inserting the inter-register transfer instruction thereat; (D) an identical instruction reference analysis processor specifying, in a plurality of execution paths, a location where the phi functions referring to a result of the identical instruction before branching are present and inserting the i

Abstract: An example of a device comprises a storage which stores data which is input from outside and to which tracking information is added, a section which detects a first reading event of first data from the storage to which the tracking information is added, a section which detects, after the first reading event, a first writing event to part of character string data to the storage, a section which detects, after the first writing event, a second reading event of second data from the storage to which the tracking information is added, a section which detects, after the second reading event, a second writing event to part of the character string data to the storage, and a section which adds, when the first reading/writing event, second reading/writing event are detected, the tracking information to data to be written to the storage by the first and second writing event.

Abstract: An example of a device comprises a storage which stores data which is input from outside and to which tracking information is added, a section which detects a first reading event of first data from the storage to which the tracking information is added, a section which detects, after the first reading event, a first writing event to part of character string data to the storage, a section which detects, after the first writing event, a second reading event of second data from the storage to which the tracking information is added, a section which detects, after the second reading event, a second writing event to part of the character string data to the storage, and a section which adds, when the first reading/writing event, second reading/writing event are detected, the tracking information to data to be written to the storage by the first and second writing event.

Abstract: An in-order state queue holds store tags as in-order information about store instructions. A temporal store cache, which uses store addresses as indexes, holds store tags and store values. A first retrieving unit retrieves store tags preceding a load tag. A second retrieving unit compares the store tag read from the temporal store cache according to the address for the load instruction with the store tag from the first retrieving unit and, when they coincide with each other, outputs a hit signal.

Abstract: An in-order state queue holds store tags as in-order information about store instructions. A temporal store cache, which uses store addresses as indexes, holds store tags and store values. A first retrieving unit retrieves store tags preceding a load tag. A second retrieving unit compares the store tag read from the temporal store cache according to the address for the load instruction with the store tag from the first retrieving unit and, when they coincide with each other, outputs a hit signal.