Patents by Inventor Shuichi Takizawa

Shuichi Takizawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11812542
    Abstract: A circuit module 2 comprises: a wiring structure 4; at least one electronic component 6a, 6b arranged on the upper surface of the wiring structure 4; an insulating resin layer 8 which is provided on the upper surface of the wiring structure 4 and in which at least one electronic component 6a, 6b is embedded; and a metal layer 10 provided on the upper surface of the insulating resin layer 8. The surface roughness of the portion S1 directly above each electronic component on the upper surface of the insulating resin layer 8 is expressed as R1. The surface roughness of the portion S2 other than the portion directly above all the electronic components on the upper surface of the insulating resin layer 8 is expressed as R2. At least one R1 satisfies the condition: R1>R2.
    Type: Grant
    Filed: February 2, 2023
    Date of Patent: November 7, 2023
    Assignee: TDK CORPORATION
    Inventors: Shuichi Takizawa, Hironori Sato, Atsushi Yoshino, Hideki Kachi
  • Publication number: 20230337371
    Abstract: Disclosed herein is an electronic circuit module that includes a circuit board, an electronic component mounted on an upper surface of the circuit board, and a mold member that covers the upper and side surfaces of the circuit board. The lower area of the side surface of the circuit board is exposed so as not to be covered with the mold member.
    Type: Application
    Filed: June 23, 2023
    Publication date: October 19, 2023
    Inventors: Shuichi TAKIZAWA, Atsushi YOSHINO, Yuki OKINO, Hiromu HARADA
  • Publication number: 20230317540
    Abstract: An electronic circuit package disclosed in the present disclosure includes: a package board having an upper surface, a bottom surface positioned on a side opposite to the upper surface, and a side surface connecting the upper and bottom surfaces; an electronic component mounted on the upper surface of the package board; a first protective layer covering the upper surface of the package board so as to embed therein the electronic component; and a second protective layer covering the side surface of the package board. The first and second protective layers contact each other.
    Type: Application
    Filed: April 4, 2023
    Publication date: October 5, 2023
    Inventors: Shuichi TAKIZAWA, Hiromu HARADA, Atsushi YOSHINO, Yuki OKINO
  • Publication number: 20230189491
    Abstract: A circuit module 2 comprises: a wiring structure 4; at least one electronic component 6a, 6b arranged on the upper surface of the wiring structure 4; an insulating resin layer 8 which is provided on the upper surface of the wiring structure 4 and in which at least one electronic component 6a, 6b is embedded; and a metal layer 10 provided on the upper surface of the insulating resin layer 8. The surface roughness of the portion S1 directly above each electronic component on the upper surface of the insulating resin layer 8 is expressed as R1. The surface roughness of the portion S2 other than the portion directly above all the electronic components on the upper surface of the insulating resin layer 8 is expressed as R2. At least one R1 satisfies the condition: R1>R2.
    Type: Application
    Filed: February 2, 2023
    Publication date: June 15, 2023
    Applicant: TDK CORPORATION
    Inventors: Shuichi TAKIZAWA, Hironori SATO, Atsushi YOSHINO, Hideki KACHI
  • Patent number: 11606888
    Abstract: A circuit module 2 comprises: a wiring structure 4; at least one electronic component 6a, 6b arranged on the upper surface of the wiring structure 4; an insulating resin layer 8 which is provided on the upper surface of the wiring structure 4 and in which at least one electronic component 6a, 6b is embedded; and a metal layer 10 provided on the upper surface of the insulating resin layer 8. The surface roughness of the portion S1 directly above each electronic component on the upper surface of the insulating resin layer 8 is expressed as R1. The surface roughness of the portion S2 other than the portion directly above all the electronic components on the upper surface of the insulating resin layer 8 is expressed as R2. At least one R1 satisfies the condition: R1>R2.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: March 14, 2023
    Assignee: TDK CORPORATION
    Inventors: Shuichi Takizawa, Hironori Sato, Atsushi Yoshino, Hideki Kachi
  • Publication number: 20220302059
    Abstract: Disclosed herein is an electronic component that includes a mounting surface having a terminal formation area and a plurality of terminal electrodes arranged in an array in the terminal formation area. The center point of the terminal formation area is offset with respect to the center point of the mounting surface. Thus, at mounting of the electronic component on a mounting substrate, a solder paste is supplied to a land pattern, and then the mounting is performed such that the center point of a mounting area and the center point of the mounting surface coincide with each other, whereby a predetermined displacement occurs between the planar positions of the land pattern and terminal electrode. This allows a void inside the solder to be released outside without involving a layout change of the land pattern.
    Type: Application
    Filed: March 4, 2022
    Publication date: September 22, 2022
    Inventors: Atsushi YOSHINO, Shuichi TAKIZAWA, Yuki OKINO, Hiromu HARADA
  • Publication number: 20220272842
    Abstract: Disclosed herein is an electric circuit module that includes a circuit board, an electronic component mounted on an upper surface of the circuit board, and a mold member that covers the upper and side surfaces of the circuit board. The lower area of the side surface of the circuit board is exposed so as not to be covered with the mold member.
    Type: Application
    Filed: February 14, 2022
    Publication date: August 25, 2022
    Inventors: Shuichi TAKIZAWA, Atsushi YOSHINO, Yuki OKINO, Hiromu HARADA
  • Publication number: 20210315137
    Abstract: A circuit module 2 comprises: a wiring structure 4; at least one electronic component 6a, 6b arranged on the upper surface of the wiring structure 4; an insulating resin layer 8 which is provided on the upper surface of the wiring structure 4 and in which at least one electronic component 6a, 6b is embedded; and a metal layer 10 provided on the upper surface of the insulating resin layer 8. The surface roughness of the portion 51 directly above each electronic component on the upper surface of the insulating resin layer 8 is expressed as R1. The surface roughness of the portion S2 other than the portion directly above all the electronic components on the upper surface of the insulating resin layer 8 is expressed as R2. At least one R1 satisfies the condition: R1>R2.
    Type: Application
    Filed: June 21, 2021
    Publication date: October 7, 2021
    Applicant: TDK CORPORATION
    Inventors: Shuichi TAKIZAWA, Hironori SATO, Atsushi YOSHINO, Hideki KACHI
  • Patent number: 11076513
    Abstract: A circuit module 2 comprises: a wiring structure 4; at least one electronic component 6a, 6b arranged on the upper surface of the wiring structure 4; an insulating resin layer 8 which is provided on the upper surface of the wiring structure 4 and in which at least one electronic component 6a, 6b is embedded; and a metal layer 10 provided on the upper surface of the insulating resin layer 8. The surface roughness of the portion S1 directly above each electronic component on the upper surface of the insulating resin layer 8 is expressed as R1. The surface roughness of the portion S2 other than the portion directly above all the electronic components on the upper surface of the insulating resin layer 8 is expressed as R2. At least one R1 satisfies the condition: R1>R2.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: July 27, 2021
    Assignee: TDK CORPORATION
    Inventors: Shuichi Takizawa, Hironori Sato, Atsushi Yoshino, Hideki Kachi
  • Patent number: 10797003
    Abstract: A circuit module 2 comprises: a wiring structure 4; an electronic component 6a, 6b arranged on the upper surface of the wiring structure 4; an insulating resin layer 8 which is provided on the upper surface of the wiring structure 4 and in which the electronic component 6a, 6b is embedded; and a metal layer 10 provided on a side surface S1 of the insulating resin layer 8 and a side surface S2 of the wiring structure 4. The surface roughness of the side surface S1 of the insulating resin layer 8 is expressed as R1. The surface roughness of the side surface S2 of the wiring structure 4 is expressed as R2. R1 and R2 differ from each other.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: October 6, 2020
    Assignee: TDK CORPORATION
    Inventors: Shuichi Takizawa, Hironori Sato, Atsushi Yoshino
  • Publication number: 20190267330
    Abstract: A circuit module 2 comprises: a wiring structure 4; an electronic component 6a, 6b arranged on the upper surface of the wiring structure 4; an insulating resin layer 8 which is provided on the upper surface of the wiring structure 4 and in which the electronic component 6a, 6b is embedded; and a metal layer 10 provided on a side surface S1 of the insulating resin layer 8 and a side surface S2 of the wiring structure 4. The surface roughness of the side surface S1 of the insulating resin layer 8 is expressed as R1. The surface roughness of the side surface S2 of the wiring structure 4 is expressed as R2. R1 and R2 differ from each other.
    Type: Application
    Filed: February 25, 2019
    Publication date: August 29, 2019
    Applicant: TDK CORPORATION
    Inventors: Shuichi TAKIZAWA, Hironori SATO, Atsushi YOSHINO
  • Publication number: 20190269046
    Abstract: A circuit module 2 comprises: a wiring structure 4; at least one electronic component 6a, 6b arranged on the upper surface of the wiring structure 4; an insulating resin layer 8 which is provided on the upper surface of the wiring structure 4 and in which at least one electronic component 6a, 6b is embedded; and a metal layer 10 provided on the upper surface of the insulating resin layer 8. The surface roughness of the portion 51 directly above each electronic component on the upper surface of the insulating resin layer 8 is expressed as R1. The surface roughness of the portion S2 other than the portion directly above all the electronic components on the upper surface of the insulating resin layer 8 is expressed as R2. At least one R1 satisfies the condition: R1>R2.
    Type: Application
    Filed: February 25, 2019
    Publication date: August 29, 2019
    Applicant: TDK CORPORATION
    Inventors: Shuichi TAKIZAWA, Hironori SATO, Atsushi YOSHINO, Hideki KACHI
  • Patent number: 10180670
    Abstract: To reliably detect a communication error status and to resolve the communication error status when reliably recovered from the error status. A count value is changed into one of up and down directions when a communication error is detected by a communication error determination unit, the count value is changed into the other direction of the up and down directions when communication being normal is detected by the communication error determination unit, a communication error status is output when the count value becomes a first threshold value, and the communication error status is resolved when the count value becomes a second threshold value different from the first threshold value.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: January 15, 2019
    Assignee: SONY CORPORATION
    Inventors: Naoyuki Sugeno, Kohki Watanabe, Shuichi Takizawa
  • Patent number: 10069311
    Abstract: A power storage device includes: power storage units each including at least one battery, the power storage units being connected in series; cell balance units connected in parallel to the respective power storage units via switches; and a control unit that performs control to charge the power storage units with a first constant current value, and, when the power storage unit having the highest voltage among the power storage units reaches a first potential, connect the corresponding one of the cell balance units to the power storage unit having the highest voltage, and switch the charging current to a second constant current value that is smaller than the first constant current value.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: September 4, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Naoyuki Sugeno, Kohki Watanabe, Masumi Terauchi, Shuichi Takizawa, Noritoshi Imamura, Koji Umetsu
  • Patent number: 10056773
    Abstract: A battery package including a power storage portion; and a control device, where the control device determines if a first temperature of the power storage portion is higher than a predetermined temperature, and if the first temperature is higher than the predetermined temperature, discharges the power storage portion at a first discharge rate.
    Type: Grant
    Filed: October 7, 2013
    Date of Patent: August 21, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Naoyuki Sugeno, Kohki Watanabe, Shuichi Takizawa, Kenji Sato, Koji Umetsu
  • Patent number: 10008862
    Abstract: There is provided a power storage device including a plurality of modules each including secondary batteries, a charging switch that controls charging to the secondary batteries, a discharging switch that controls discharging of the secondary batteries, and a voltage measuring unit that measures a voltage of the module, and a switch control unit that controls one or both of the charging switch and the discharging switch. The modules are connected in parallel. The switch control unit maintains an on state of the discharging switch for at least one of the modules for a predetermined period, and controls the charging switch of the module in which a maximum module charging current estimated based on the voltage of the module is a predetermined value or less, to be in an on state.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: June 26, 2018
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Shuichi Takizawa, Naoyuki Sugeno, Koji Umetsu, Eiji Kumagai, Bunya Sato, Aniket Khade, Tatsuya Adachi, Atsushi Chinen, Hisato Asai, Kohki Watanabe
  • Patent number: 9439288
    Abstract: An electronic module is provided with a circuit board 2, a chip component 3 surface-mounted on the circuit board 2 and a mold member 4 that seals the chip component 3. The circuit board 2 includes a land 7 and a resist pattern 8A that partially covers the land 7. The chip component 3 has a bottom electrode 6b and a side electrode 6c. The resist pattern 8A has an overlapped portion overlapped with the bottom electrode 6b of the chip component 3 in a planar view. A portion of the mold member 4 is filled at least in a first gap D1 between the resist pattern 8A and the first solder portion 10a.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: September 6, 2016
    Assignee: TDK Corporation
    Inventors: Shuichi Takizawa, Kenichi Kawabata
  • Publication number: 20160218528
    Abstract: A power storage device includes: power storage units each including at least one battery, the power storage units being connected in series; cell balance units connected in parallel to the respective power storage units via switches; and a control unit that performs control to charge the power storage units with a first constant current value, and, when the power storage unit having the highest voltage among the power storage units reaches a first potential, connect the corresponding one of the cell balance units to the power storage unit having the highest voltage, and switch the charging current to a second constant current value that is smaller than the first constant current value.
    Type: Application
    Filed: June 26, 2014
    Publication date: July 28, 2016
    Inventors: Naoyuki SUGENO, Kohki WATANABE, Masumi TERAUCHI, Shuichi TAKIZAWA, Noritoshi IMAMURA, Koji UMETSU
  • Publication number: 20160049813
    Abstract: There is provided a power storage device including a plurality of modules each including secondary batteries, a charging switch that controls charging to the secondary batteries, a discharging switch that controls discharging of the secondary batteries, and a voltage measuring unit that measures a voltage of the module, and a switch control unit that controls one or both of the charging switch and the discharging switch. The modules are connected in parallel. The switch control unit maintains an on state of the discharging switch for at least one of the modules for a predetermined period, and controls the charging switch of the module in which a maximum module charging current estimated based on the voltage of the module is a predetermined value or less, to be in an on state.
    Type: Application
    Filed: March 6, 2014
    Publication date: February 18, 2016
    Inventors: Shuichi TAKIZAWA, Naoyuki SUGENO, Koji UMETSU, Eiji KUMAGAI, Bunya SATO, Aniket KHADE, Tatsuya ADACHI, Atsushi CHINEN, Hisato ASAI, Kohki WATANABE
  • Publication number: 20150295448
    Abstract: A battery package including a power storage portion; and a control device, where the control device determines if a first temperature of the power storage portion is higher than a predetermined temperature, and if the first temperature is higher than the predetermined temperature, discharges the power storage portion at a first discharge rate.
    Type: Application
    Filed: October 7, 2013
    Publication date: October 15, 2015
    Inventors: Naoyuki SUGENO, Kohki WATANABE, Shuichi TAKIZAWA, Kenji SATO, Koji UMETSU