Patents by Inventor Shuiyuan Huang
Shuiyuan Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11957065Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A superconducting integrated circuit comprising a superconducting stud via, a kinetic inductor, and a capacitor may be formed. Forming a superconducting stud via in a superconducting integrated circuit may include masking with a hard mask and masking with a soft mask. Forming a superconducting stud via in a superconducting integrated circuit may include depositing a dielectric etch stop layer. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by an electrical vernier. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by a chain of electrical verniers and a Wheatstone bridge. A superconducting integrated circuit with three or more metal layers may include an enclosed, matched, on-chip transmission line. A metal wiring layer in a superconducting integrated circuit may be encapsulated.Type: GrantFiled: May 17, 2021Date of Patent: April 9, 2024Assignee: 1372934 B.C. LTD.Inventors: Shuiyuan Huang, Byong H. Oh, Douglas P. Stadtler, Edward G. Sterpka, Paul I. Bunyk, Jed D. Whittaker, Fabio Altomare, Richard G. Harris, Colin C. Enderud, Loren J. Swenson, Nicolas C. Ladizinsky, Jason J. Yao, Eric G. Ladizinsky
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Patent number: 11856871Abstract: Systems and methods for fabricating a superconducting integrated circuit that includes wiring layers comprising low-noise material are described. A superconducting integrated circuit can be implemented in a computing system that includes a quantum processor. Such a superconducting integrated circuit includes a first set of one or more wiring layers that form a noise-susceptible superconducting device that can decrease processor when exposed to noise. The superconducting integrated circuit can further include a second set of one or more wiring layers that form a superconducting device that is less susceptible to noise. Fabricating a superconducting device that contains low-noise material can include depositing and patterning a wiring layer comprising a first material that is superconductive in a respective range of temperatures and depositing and patterning a different wiring layer comprising a second material that is superconductive in a respective range of temperatures.Type: GrantFiled: February 25, 2022Date of Patent: December 26, 2023Assignee: D-WAVE SYSTEMS INC.Inventors: Trevor M. Lanting, Danica W. Marsden, Byong Hyop Oh, Eric G. Ladizinsky, Shuiyuan Huang, J. Jason Yao, Douglas P. Stadtler
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Publication number: 20220263007Abstract: Systems and methods for fabricating a superconducting integrated circuit that includes wiring layers comprising low-noise material are described. A superconducting integrated circuit can be implemented in a computing system that includes a quantum processor. Such a superconducting integrated circuit includes a first set of one or more wiring layers that form a noise-susceptible superconducting device that can decrease processor when exposed to noise. The superconducting integrated circuit can further include a second set of one or more wiring layers that form a superconducting device that is less susceptible to noise. Fabricating a superconducting device that contains low-noise material can include depositing and patterning a wiring layer comprising a first material that is superconductive in a respective range of temperatures and depositing and patterning a different wiring layer comprising a second material that is superconductive in a respective range of temperatures.Type: ApplicationFiled: February 25, 2022Publication date: August 18, 2022Inventors: Trevor M. Lanting, Danica W. Marsden, Byong Hyop Oh, Eric G. Ladizinsky, Shuiyuan Huang, J. Jason Yao, Douglas P. Stadtler
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Publication number: 20210384406Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A superconducting integrated circuit comprising a superconducting stud via, a kinetic inductor, and a capacitor may be formed. Forming a superconducting stud via in a superconducting integrated circuit may include masking with a hard mask and masking with a soft mask. Forming a superconducting stud via in a superconducting integrated circuit may include depositing a dielectric etch stop layer. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by an electrical vernier. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by a chain of electrical verniers and a Wheatstone bridge. A superconducting integrated circuit with three or more metal layers may include an enclosed, matched, on-chip transmission line. A metal wiring layer in a superconducting integrated circuit may be encapsulated.Type: ApplicationFiled: May 17, 2021Publication date: December 9, 2021Inventors: Shuiyuan Huang, Byong H. Oh, Douglas P. Stadtler, Edward G. Sterpka, Paul I. Bunyk, Jed D. Whittaker, Fabio Altomare, Richard G. Harris, Colin C. Enderud, Loren J. Swenson, Nicolas C. Ladizinsky, Jason J. Yao, Eric G. Ladizinsky
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Patent number: 11038095Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A superconducting integrated circuit comprising a superconducting stud via, a kinetic inductor, and a capacitor may be formed. Forming a superconducting stud via in a superconducting integrated circuit may include masking with a hard mask and masking with a soft mask. Forming a superconducting stud via in a superconducting integrated circuit may include depositing a dielectric etch stop layer. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by an electrical vernier. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by a chain of electrical verniers and a Wheatstone bridge. A superconducting integrated circuit with three or more metal layers may include an enclosed, matched, on-chip transmission line. A metal wiring layer in a superconducting integrated circuit may be encapsulated.Type: GrantFiled: January 31, 2018Date of Patent: June 15, 2021Assignee: D-WAVE SYSTEMS INC.Inventors: Shuiyuan Huang, Byong H. Oh, Douglas P. Stadtler, Edward G. Sterpka, Paul I. Bunyk, Jed D. Whittaker, Fabio Altomare, Richard G. Harris, Colin C. Enderud, Loren J. Swenson, Nicolas C. Ladizinsky, Jason J. Yao, Eric G. Ladizinsky
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Publication number: 20200152851Abstract: Systems and methods for fabricating a superconducting integrated circuit that includes wiring layers comprising low-noise material are described. A superconducting integrated circuit can be implemented in a computing system that includes a quantum processor. Such a superconducting integrated circuit includes a first set of one or more wiring layers that form a noise-susceptible superconducting device that can decrease processor when exposed to noise. The superconducting integrated circuit can further include a second set of one or more wiring layers that form a superconducting device that is less susceptible to noise. Fabricating a superconducting device that contains low-noise material can include depositing and patterning a wiring layer comprising a first material that is superconductive in a respective range of temperatures and depositing and patterning a different wiring layer comprising a second material that is superconductive in a respective range of temperatures.Type: ApplicationFiled: November 12, 2019Publication date: May 14, 2020Inventors: Trevor M. Lanting, Danica W. Marsden, Byong Hyop Oh, Eric G. Ladizinsky, Shuiyuan Huang, J. Jason Yao, Douglas P. Stadtler
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Publication number: 20200144476Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A superconducting integrated circuit comprising a superconducting stud via, a kinetic inductor, and a capacitor may be formed. Forming a superconducting stud via in a superconducting integrated circuit may include masking with a hard mask and masking with a soft mask. Forming a superconducting stud via in a superconducting integrated circuit may include depositing a dielectric etch stop layer. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by an electrical vernier. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by a chain of electrical verniers and a Wheatstone bridge. A superconducting integrated circuit with three or more metal layers may include an enclosed, matched, on-chip transmission line. A metal wiring layer in a superconducting integrated circuit may be encapsulated.Type: ApplicationFiled: January 31, 2018Publication date: May 7, 2020Inventors: Shuiyuan Huang, Byong H. Oh, Douglas P. Stadtler, Edward G. Sterpka, Paul I. Bunyk, Jed D. Whittaker, Fabio Altomare, Richard G. Harris, Colin C. Enderud, Loren J. Swenson, Nicolas C. Ladizinsky, Jason J. Yao, Eric G. Ladizinsky
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Patent number: 8766230Abstract: Non-volatile multi-bit memory with programmable capacitance is disclosed. Illustrative data memory units include a substrate including a source region and a drain region; and a gate stack structure over the substrate and between the source region and drain region. The gate stack structure includes a first solid electrolyte cell and a second solid electrolyte cell. The solid electrolyte cells having a capacitance that is controllable between at least two states. A gate contact layer is electrically coupled to a voltage source. The first solid electrolyte cell and the second solid electrolyte cell separate the gate contact layer from the substrate.Type: GrantFiled: August 17, 2010Date of Patent: July 1, 2014Assignee: Seagate Technology LLCInventors: Xuguang Wang, Shuiyuan Huang, Dimitar V. Dimitrov, Michael Xuefei Tang, Song S. Xue
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Patent number: 8487390Abstract: A magnetic memory element that has a stress-induced magnetic anisotropy. The memory element has a ferromagnetic free layer having a switchable magnetization orientation switchable, a ferromagnetic reference layer having a pinned magnetization orientation, and a non-magnetic spacer layer therebetween. The free layer may be circular, essentially circular or nearly circular.Type: GrantFiled: April 6, 2009Date of Patent: July 16, 2013Assignee: Seagate Technology LLCInventors: Dimitar V. Dimitrov, Ivan Petrov Ivanov, Shuiyuan Huang, Antoine Khoueir, Brian Lee, John Daniel Stricklin, Olle Gunnar Heinonen, Insik Jin
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Patent number: 8476721Abstract: A transistor device includes a magnetic field source adapted to deflect a flow of free electron carriers within a channel of the device, between a source region and a drain region thereof. According to preferred configurations, the magnetic field source includes a magnetic material layer extending over a side of the channel that is opposite a gate electrode of the transistor device.Type: GrantFiled: April 18, 2011Date of Patent: July 2, 2013Assignee: Seagate Technology LLCInventors: Yang Li, Insik Jin, Harry Liu, Song S. Xue, Shuiyuan Huang, Michael X. Tang
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Patent number: 8399908Abstract: Methods for making a programmable metallization memory cell are disclosed.Type: GrantFiled: January 11, 2012Date of Patent: March 19, 2013Assignee: Seagate Technology LLCInventors: Haiwen Xi, Ming Sun, Dexin Wang, Shuiyuan Huang, Michael Tang, Song S. Xue
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Patent number: 8334165Abstract: Methods for making a programmable metallization memory cell are disclosed.Type: GrantFiled: April 16, 2010Date of Patent: December 18, 2012Assignee: Seagate Technology LLCInventors: Haiwen Xi, Ming Sun, Dexin Wang, Shuiyuan Huang, Michael Tang, Song S. Xue
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Publication number: 20120104348Abstract: Methods for making a programmable metallization memory cell are disclosed.Type: ApplicationFiled: January 11, 2012Publication date: May 3, 2012Applicant: SEAGATE TECHNOLOGY LLCInventors: Haiwen Xi, Ming Sun, Dexin Wang, Shuiyuan Huang, Michael Tang, Song S. Xue
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Patent number: 8097902Abstract: A programmable metallization memory cell that has an apertured insulating layer comprising at least one aperture therethrough positioned between the active electrode and the inert electrode. Superionic clusters are present within the at least one aperture, and may extend past the at least one aperture. Also, methods for making a programmable metallization memory cell are disclosed.Type: GrantFiled: July 10, 2008Date of Patent: January 17, 2012Assignee: Seagate Technology LLCInventors: Haiwen Xi, Ming Sun, Dexin Wang, Shuiyuan Huang, Michael Tang, Song S. Xue
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Publication number: 20110267873Abstract: Non-volatile memory with programmable capacitance is disclosed. Illustrative data memory units include a substrate including a source region and a drain region. A first insulating layer is over the substrate. A second insulating layer is over the substrate and between the source region and drain region. A solid electrolyte layer is between the first insulating layer and second insulating layer. The solid electrolyte layer has a capacitance that is controllable between at least two states. A first electrode is electrically coupled to a first side of the solid electrolyte layer and is electrically coupled to a voltage source. A second electrode is electrically coupled to a second side of the solid electrolyte layer and is electrically coupled to the voltage source. Multi-bit memory units are also disclosed.Type: ApplicationFiled: June 2, 2011Publication date: November 3, 2011Applicant: SEAGATE TECHNOLOGY LLCInventors: Shuiyuan Huang, Xuguang Wang, Dimitar V. Dimitrov, Michael Tang, Song S. Xue
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Publication number: 20110193148Abstract: A transistor device includes a magnetic field source adapted to deflect a flow of free electron carriers within a channel of the device, between a source region and a drain region thereof. According to preferred configurations, the magnetic field source includes a magnetic material layer extending over a side of the channel that is opposite a gate electrode of the transistor device.Type: ApplicationFiled: April 18, 2011Publication date: August 11, 2011Applicant: SEAGATE TECHNOLOGY LLCInventors: Yang Li, Insik Jin, Harry Liu, Song S. Xue, Shuiyuan Huang, Michael X. Tang
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Patent number: 7977722Abstract: Non-volatile memory with programmable capacitance is disclosed. Illustrative data memory units include a substrate including a source region and a drain region. A first insulating layer is over the substrate. A second insulating layer is over the substrate and between the source region and drain region. A solid electrolyte layer is between the first insulating layer and second insulating layer. The solid electrolyte layer has a capacitance that is controllable between at least two states. A first electrode is electrically coupled to a first side of the solid electrolyte layer and is electrically coupled to a voltage source. A second electrode is electrically coupled to a second side of the solid electrolyte layer and is electrically coupled to the voltage source. Multi-bit memory units are also disclosed.Type: GrantFiled: May 20, 2008Date of Patent: July 12, 2011Assignee: Seagate Technology LLCInventors: Xuguang Wang, Shuiyuan Huang, Dimitar V. Dimitrov, Michael Xuefei Tang, Song S. Xue
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Patent number: 7965538Abstract: Apparatus and method for providing overcurrent protection to a resistive random access memory (RRAM) cell during an RRAM formation process used to prepare the cell for normal read and write operations. In accordance with various embodiments, the RRAM cell is connected between a first control line and a second control line, and an active protection device (APD) is connected between the second control line and an electrical ground terminal. A formation current is applied through the RRAM cell, and an activation voltage is concurrently applied to the APD to maintain a maximum magnitude of the formation current below a predetermined threshold level.Type: GrantFiled: July 13, 2009Date of Patent: June 21, 2011Assignee: Seagate Technology LLCInventors: Yongchul Ahn, Antoine Khoueir, Shuiyuan Huang, Peter Nicholas Manos, Maroun Khoury
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Patent number: 7948045Abstract: A transistor device includes a magnetic field source adapted to deflect a flow of free electron carriers within a channel of the device, between a source region and a drain region thereof. According to preferred configurations, the magnetic field source includes a magnetic material layer extending over a side of the channel that is opposite a gate electrode of the transistor device.Type: GrantFiled: August 18, 2008Date of Patent: May 24, 2011Assignee: Seagate Technology LLCInventors: Yang Li, Insik Jin, Harry Liu, Song S. Xue, Shuiyuan Huang, Michael X. Tang
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Publication number: 20110007552Abstract: Apparatus and method for providing overcurrent protection to a resistive random access memory (RRAM) cell during an RRAM formation process used to prepare the cell for normal read and write operations. In accordance with various embodiments, the RRAM cell is connected between a first control line and a second control line, and an active protection device (APD) is connected between the second control line and an electrical ground terminal.Type: ApplicationFiled: July 13, 2009Publication date: January 13, 2011Applicant: SEAGATE TECHNOLOGY LLCInventors: Yongchul Ahn, Antoine Khoueir, Shuiyuan Huang, Peter Nicholas Manos, Maroun Khoury