Abstract: A scan driver circuit includes a pull-up unit and a bootstrap unit arranged on a base. The pull-up unit includes a pull-up thin-film transistor for supplying a scan drive signal. The bootstrap unit includes a bootstrap capacitor electrically connected with the pull-up thin-film transistor. The pull-up thin-film transistor includes a gate electrode, a first insulation layer, and a source electrode and a drain electrode stacked in sequence from the base. The bootstrap capacitor includes first and conductive electrodes. The first conductive electrode and the source electrode are arranged on the same layer and are electrically connected together. A second insulation layer is arranged between the second conductive electrode and the second electrode. The second conductive electrode is electrically connected, through a first via that extends through the second insulation layer and the first insulation layer, to the gate electrode. An array substrate and a display device are also provided.

Abstract: A scan driver circuit includes a pull-up unit and a bootstrap unit arranged on a base. The pull-up unit includes a pull-up thin-film transistor for supplying a scan drive signal. The bootstrap unit includes a bootstrap capacitor electrically connected with the pull-up thin-film transistor. The pull-up thin-film transistor includes a gate electrode, a first insulation layer, and a source electrode and a drain electrode stacked in sequence from the base. The bootstrap capacitor includes first and conductive electrodes. The first conductive electrode and the source electrode are arranged on the same layer and are electrically connected together. A second insulation layer is arranged between the second conductive electrode and the second electrode. The second conductive electrode is electrically connected, through a first via that extends through the second insulation layer and the first insulation layer, to the gate electrode. An array substrate and a display device are also provided.

Abstract: A thin film transistor, a TFT substrate, and a display panel are provided. The TFT includes a gate, a source, and a drain. The source is a first bending structure. The drain is a second bending structure. The gate is a third bending structure. The first bending structure of the source and the second bending structure of the drain are arranged opposite. The third bending structure of the gate is arranged between the first bending structure of the source and the second bending structure of the drain. The present disclosure facilitates fabrication of a narrow bezel of a display panel.

Abstract: The present disclosure discloses a manufacturing method of a thin film transistor, including: forming a gate layer on a substrate; forming a gate insulating layer on the gate layer and the substrate; forming an active layer on the gate insulating layer; and simultaneously forming a source and a drain formed on the active layer by a combination of a chemical plating method and a lift-off method. In the present disclosure, the chemical plating method is combined with the lift-off method, so that the wet-etching method is not used for forming the source and the drain, and thus the IGZO at the channel is not required to be protected by the etching-stop-layer. Therefore, while simplifying the production process, but also can reduce costs.

Abstract: A GOA driving circuit includes a plurality of cascaded GOA units and outputs a gate driving signal to an Nth-stage horizontal scanning line of a display region by an Nth-stage GOA unit. The Nth-stage GOA unit includes a pull-up unit, a pull-up control unit, a pull-down unit, a pull-down sustaining unit, a download unit, and a bootstrap capacitor unit. The pull-up unit, the pull-down unit, the pull-down sustaining unit, and the bootstrap capacitor unit are respectively electrically connected with a first node and an Nth-stage horizontal scanning line. The pull-up control unit and the download unit are electrically connected with the first node. N is a positive integer. The Nth-stage GOA unit further includes a forced pull-down unit, which is used to force the first node to low level when clock signals are disappeared. A LCD device is also provided.

Abstract: The present disclosure relates to a bidirectional shift register unit, a bidirectional shift register, and a display panel, wherein the bidirectional shift register unit includes: an pull-up circuit is configured to transform first clock signals into scanning signals outputting at a current level, an pull-up control circuit is configured with a forward pull-up sub-circuit and a backward pull-up sub-circuit respectively configured to pull up a potential of a control end of the pull-up circuit when a forward scanning process or a backward scanning process is conducted, a pull-down circuit and a pull-down maintaining circuit are respectively configured to pull down and continuously pull down the potential of the control end of the pull-up circuit and the scanning signals outputting at the current level during a pull-down phase. As such, a bidirectional scanning process may be achieved.

Abstract: Related to is the technical field of display panels, and in particular to a thin film transistor and a method for manufacturing the same. The thin film transistor provided on a substrate includes a drain, a source, a gate, and an active layer. The drain and the source are in a comb-like shape and are connected with the active layer through a first via hole and a second via hole, respectively. Such arrangement enables a width of a channel formed between the drain and the source to be increased and a layout scale of the thin film transistor to be reduced at the same time, whereby space is saved. When used in a GOA circuit or other circuits, the thin film transistor is helpful to achievement of a narrow-bezel design of a display panel.

Abstract: The present disclosure discloses a manufacturing method of a thin film transistor, including: forming a gate layer on a substrate; forming a gate insulating layer on the gate layer and the substrate; forming an active layer on the gate insulating layer; and simultaneously forming a source and a drain formed on the active layer by a combination of a chemical plating method and a lift-off method. In the present disclosure, the chemical plating method is combined with the lift-off method, so that the wet-etching method is not used for forming the source and the drain, and thus the IGZO at the channel is not required to be protected by the etching-stop-layer. Therefore, while simplifying the production process, but also can reduce costs.

Abstract: A scan driving circuit and a display panel are disclosed. A scan driving unit includes a pull-up control circuit configured for receiving a stage transmission signal of the previous two stages to charge a pull-up control signal node. A first reset circuit receives an input signal, a first clock signal and a second clock signal to reset the pull-up control signal node, wherein the input signal is a DC voltage. A pull-down holding circuit receives a low frequency clock signal and a second low frequency clock signal to hold the electric potential of the pull-up control signal node. A pull-down circuit receives a scan driving signal of the next two stages to pull down the electric potential of the pull-up control signal node. A pull-up circuit receives the first clock signal to output a stage transmission signal and a scan driving signal of the current stage.

Abstract: A scan driving circuit and a display panel are disclosed. A scan driving unit includes a pull-up control circuit configured for receiving a stage transmission signal of the previous two stages to charge a pull-up control signal node. A first reset circuit receives an input signal, a first clock signal and a second clock signal to reset the pull-up control signal node, wherein the input signal is a DC voltage. A pull-down holding circuit receives a low frequency clock signal and a second low frequency clock signal to hold the electric potential of the pull-up control signal node. A pull-down circuit receives a scan driving signal of the next two stages to pull down the electric potential of the pull-up control signal node. A pull-up circuit receives the first clock signal to output a stage transmission signal and a scan driving signal of the current stage.

Abstract: The present application discloses a pull down maintaining circuit, comprising: a first switch transistor, an input terminal is connected to a first direct current power source, and an output terminal outputting a scanning signal of the Nth level scanning line; a second switch transistor, an input terminal is connected to the first direct current power source, and an output terminal outputting a scanning electric level signal of the Nth level scanning line; a control unit for controlling the first and the second switch transistors to turn off in accordance with a low voltage outputted from the first and the second direct current power source, and the third direct current power source, and to control the first and the second switch transistors to normally turn on in accordance with a high voltage is outputted from the first and the second direct current power source, and the third direct current power source.

Abstract: Related to is the technical field of display panels, and in particular to a thin film transistor and a method for manufacturing the same. The thin film transistor provided on a substrate includes a drain, a source, a gate, and an active layer. The drain and the source are in a comb-like shape and are connected with the active layer through a first via hole and a second via hole, respectively. Such arrangement enables a width of a channel formed between the drain and the source to be increased and a layout scale of the thin film transistor to be reduced at the same time, whereby space is saved. When used in a GOA circuit or other circuits, the thin film transistor is helpful to achievement of a narrow-bezel design of a display panel.

Abstract: The present disclosure relates to a bidirectional shift register unit, a bidirectional shift register, and a display panel, wherein the bidirectional shift register unit includes: an pull-up circuit is configured to transform first clock signals into scanning signals outputting at a current level, an pull-up control circuit is configured with a forward pull-up sub-circuit and a backward pull-up sub-circuit respectively configured to pull up a potential of a control end of the pull-up circuit when a forward scanning process or a backward scanning process is conducted, a pull-down circuit and a pull-down maintaining circuit are respectively configured to pull down and continuously pull down the potential of the control end of the pull-up circuit and the scanning signals outputting at the current level during a pull-down phase. As such, a bidirectional scanning process may be achieved.

Abstract: The present disclosure relates to a gate driving circuit including N number of cascaded-connected GOA driving units, wherein the GOA driving units at each of the levels includes a pull-up control circuit, a pull-up circuit, a level transfer circuit, a boast capacitor, and a pull-down holding circuit. The pull-down holding circuit of the GOA driving unit of the n-th level and the pull-down holding circuit of the GOA driving unit of the (n+1)-th level are turned on alternatedly. The pull-down holding circuit of die GOA driving unit of the n-th level may keep the potential of the node within the GOA driving units at the n-th and the (n+1)-th level in the off state, wherein n=1, 3, 5, . . . , N?1, and N is an even number greater than one. The present disclosure also relates to a LCD including the above gate driving circuit.

Abstract: A GOA driving circuit includes a plurality of cascaded GOA units and outputs a gate driving signal to an Nth-stage horizontal scanning line of a display region by an Nth-stage GOA unit. The Nth-stage GOA unit includes a pull-up unit, a pull-up control unit, a pull-down unit, a pull-down sustaining unit, a download unit, and a bootstrap capacitor unit. The pull-up unit, the pull-down unit, the pull-down sustaining unit, and the bootstrap capacitor unit are respectively electrically connected with a first node and an Nth-stage horizontal scanning line. The pull-up control unit and the download unit are electrically connected with the first node. N is a positive integer. The Nth-stage GOA unit further includes a forced pull-down unit, which is used to force the first node to low level when clock signals are disappeared. A LCD device is also provided.

Abstract: The present disclosure provides a GOA circuit and a liquid crystal display, the GOA circuit includes: a pull-up circuit; a scan output terminal; a pull-up control circuit including: a second switch tube; a third switch tube having a first connection terminal coupled to the second connection terminal of the second switch tube and a second connection terminal coupled to the control terminal of the first switch tube; a fourth switch tube having a control terminal coupled to the control terminal of the first switch tube, a first connection terminal coupled to the first connection terminal of the third switch tube and a second connection terminal coupled to the scan output terminal. In this way, the disclosure can avoid the problem that the transistor is erroneously turned on or off due to the threshold drift and the circuit output error is caused.

Abstract: The present disclosure relates to a gate driver on array (GOA) circuit and a liquid crystal display (LCD). The GOA circuit includes a plurality of cascaded-connected GOA units connected, and the GOA unit at N-th level includes: a pull-up controlling module, a pull-up module, a down-transfer module, a bootstrap capacitor module, a pull-down maintaining module, a pull-down module and a controlling module. The controlling module respectively connects with the pull-down maintaining module and the adjacent GOA unit, and the controlling module is configured to accelerate a pull-down speed of the pull-down maintaining module by increasing a discharge path of the pull-down maintaining module on the GOA unit at the next level. As such, the response speed of the pull-down maintaining module may be improved, so as to improve the performance of the pull-down maintaining module.

Abstract: A pixel array substrate and a display device are disclosed. Wherein, an arrangement direction starting from the first pixel to the second pixel in the pixel unit is defined as a first direction, a conductive sequence of the scanning lines is defined as a second direction. In each of the at least two display regions, the first direction and the second direction are the same, in different display regions, the second directions are the same. The present invention can avoid that in adjacent pixel units, a coupling effect among pixels having different capacitances will make a middle region of the display region to have a larger brightness.

Abstract: The present disclosure relates to a gate driver on array (GOA) circuit and a liquid crystal display (LCD). The GOA circuit includes a plurality of cascaded-connected GOA units connected, and the GOA unit at N-th level includes: a pull-up controlling module, a pull-up module, a down-transfer module, a bootstrap capacitor module, a pull-down maintaining module, a pull-down module and a controlling module. The controlling module respectively connects with the pull-down maintaining module and the adjacent GOA unit, and the controlling module is configured to to accelerate a pull-down speed of the pull-down maintaining module by increasing a discharge path of the pull-down maintaining module on the GOA unit at the next level. As such, the response speed of the pull-down maintaining module may be improved, so as to improve the performance of the pull-down maintaining module.

Abstract: A thin film transistor, a TFT substrate, and a display panel are provided. The TFT includes a gate, a source, and a drain. The source is a first bending structure. The drain is a second bending structure. The gate is a third bending structure. The first bending structure of the source and the second bending structure of the drain are arranged opposite. The third bending structure of the gate is arranged between the first bending structure of the source and the second bending structure of the drain. The present disclosure facilitates fabrication of a narrow bezel of a display panel.