Abstract: There is provided a highly reliable transmission/reception integrated radio-frequency apparatus which can achieve a high communication quality in a cable modem. A reception RF signal is input to a reception system block via an input/output terminal, converted to an intermediate-frequency signal, and output from a terminal. An output terminal of a transmission processing section of a transmission system block is connected to the input/output terminal via an overvoltage protection circuit, a high-pass filter functioning as a countermeasure to overvoltage, and a low-pass filter for suppressing harmonics produced from the high-pass filter.

Abstract: An optical storage element capable of writing and/or erasing information by irradiation with light, which element comprises a first unit composed of a first photo-induced phase-transition substance that gets stable in a first state, and a second unit composed of a second photo-induced phase transition substance that gets stable in a second state, the first and second units being arrayed in a superlattice-like form.

Abstract: A double super tuner for receiving television signals from conventional broadcast, CATV, satellite broadcast, and HDTV. A first frequency converter converts an input high-frequency signal in a first intermediate frequency band signal based on a first local oscillator signal. The output of the first frequency converter is band-pass filtered by a dielectric filter. A second frequency converter converts the output of the dielectric filter into a second intermediate frequency band signal based on a second local oscillator signal.

Abstract: In the image decoding apparatus, the maximum absolute value of difference values of adjacent pixel data of each pixel block of image data is obtained as a feature of the image data. An optimum quantizing coefficient is selected for the maximum absolute value of the difference value. With the selected quantizing coefficient, the maximum absolute value is quantized. When the difference values of adjacent pixel data of each pixel block of image data concentrate in the vicinity of "0", they are quantized with a smaller quantizing coefficient. Thus, with an optimum quantizing coefficient, each pixel block of image data can be quantized. Consequently, quantizing errors can be reduced.

Abstract: A frame combining apparatus, having a plurality of decoding means for decoding frame data for each of a plurality of sub-frames through a decoding process opposite to a coding process when a plurality of coded data streams obtained by coding frame data of a frame divided into a plurality of sub-frames are input, a synchronizing means for generating external synchronizing data for defining output timings of decoded outputs from a plurality of decoding means, and a delaying means for generating more than one external synchronizing data delayed by a delay time corresponding to a plurality of sub-frames in response to the division of a frame and to give the external synchronizing data from the synchronizing means and external synchronizing data having a delay time corresponding to the divided sub-frames out of more than one delayed external synchronizing data to decoding means corresponding to the sub-frames, respectively.

Abstract: A tuner circuit comprising a first frequency conversion means 14 for converting a high frequency input signal into a first intermediate frequency signal according to a first local oscillation signal, a second frequency conversion means 19 for converting the first intermediate frequency signal from the first frequency conversion means 14 into a second intermediate frequency signal according to a second local oscillation signal, a first PLL means 24 for controlling the first local oscillation signal so as to synchronize the phase of the signal with that of a reference oscillation signal having a fixed frequency, a second PLL means 31 for controlling the second local oscillation signal so as to synchronize the phase of the signal with that of a reference oscillation signal. In the first PLL means 24, a phase comparison frequency is set to a frequency higher than a specified value. In the second PLL means 31, a phase comparison frequency is set to a frequency lower than a specified value.

Abstract: A variable length code recording/playback apparatus, which by encoding intra-frame data and inter-frame data in variable length code, records them as recorded codes on tracks of a prescribed recording medium and playbacks them, includes a data rearranger for recording the data in areas to be played back at least two specific speed mode playbacks on the tracks by rearranging prescribed data out of the data encoded in variable length code, a variable length decoder for playing back the data recorded on the recording medium and decoding them in variable length code, a data rearrangement canceller for controlling and restoring the time series of the output of the variable length decoder to the original data train before the rearrangement, and a decoder for constructing a playback picture from the decoded outputs for several frames in the specific speed mode playback by decoding the output of this data rearrangment canceller.

Abstract: An encoded data recording apparatus with high speed reproduction capability, which by encoding intra-frame data and inter-frame data in variable length code, records them as recorded codes on prescribed locations of tracks of a recording medium and plays them back, which includes a data rearranger for recording the data in areas to be played back at least two specific speed mode playbacks on the tracks by rearranging prescribed data out of the data encoded in variable length code, a variable length decoder for playing back the data recorded on the recording medium and decoding it in variable length code, a data restorer for controlling and restoring the time series of the output of the variable length decoder to the original data train before the rearrangement, and a decoder for constructing a playback picture from the decoded outputs for several frames in the specific speed mode playback by decoding the output of this data restorer.

Abstract: An apparatus for controlling a display memory for storing decoded picture data is disclosed, that comprises a data dividing portion for dividing decoded picture data as one macroblock in a vertical direction, a write address generator for generating the binary value of a write address necessary for writing the divided picture data to the display memory, a slice counter for counting the number of slice lines of picture data that has been written to the display memory, a rotate-shifter for rotating and shifting the binary value of the generated write address to the left by a first bit number corresponding to the number of slice lines counted, a means for writing the divided picture data to the display memory corresponding to the write address that has been rotated and shifted, a read address generator for generating the binary value of a read address necessary to read picture data from the display memory, a rotate-shifter for rotating and shifting the binary value of the generated read address to the left by a

Abstract: A coding data is performed in decoding by a stream decoding circuit, an IDCT circuit and an MC circuit. An AGU stores decoding data from the MC circuit to a memory. Regarding the decoding data of a B picture, the AGU writes only the decoding data which are necessary for image display, to a B picture region. Thus, a room occurs in a memory capacity. It is possible to hold the decoding data of the B picture through 2 field periods of time. It is possible to read twice the same decoding data, for display processing. Thus, frame interpolation processing is made possible, and it is possible to obtain a magnified image having high image quality.

Abstract: A data packet recording apparatus according to a first aspect of the present invention is comprised of: a trick play packet generator for generating trick play data by extracting one or plural types of prescribed date packets from an input data packet train comprising plural types of time-division multiplexed data in a prescribed number or packets based on an identification signal inserted for every packet and outputting a trick play data packet train by packetizing the generated trick play data; an identification table packet inserter for separating and retaining an identification table packet contained in the input data packet train for discriminating the identification signal and outputting the identification table packet into the trick play data packet train several times; and a recording circuit which is capable of recording the output of the identification table packet inserting means in trick play data recording areas at specified track positions.

Abstract: A double super tuner for receiving television signals from conventional broadcast, CATV, satellite broadcast, and HDTV. A first frequency converter converts an input high-frequency signal in a first intermediate frequency band signal based on a first local oscillator signal. The output of the first frequency converter is band-pass filtered by a dielectric filter. A second frequency converter converts the output of the dielectric filter into a second intermediate frequency band signal based on a second local oscillator signal.

Abstract: A variable length code recording/playback apparatus, which by encoding intra-frame data and inter-frame data in variable length code, records them as recorded codes on prescribed locations of tracks of a recording medium and plays them back, which includes a data rearrange for recording the data in areas to be played back at least two specific speed mode playbacks on the tracks by rearranging prescribed data out of the data encoded in variable length code, a variable length decoder for playing back the data recorded on the recording medium and decoding it in variable length code, a data restorer for controlling and restoring the time series of the output of the variable length decoder to the original data train before the rearrangement, and a decoder for constructing a playback picture from the decoded outputs for several frames in the specific speed mode playback by decoding the output of this data restorer.

Abstract: A digital data receiver comprising a first frequency converter for converting a high frequency digital orthogonal modulation signal into a first intermediate frequency signal based on a first local oscillation signal, a second frequency converter for converting the first intermediate frequency signal into a second intermediate frequency signal based on a second local oscillation signal, and a demodulator for performing a orthogonal demodulation to the second intermediate frequency signal based on a third local oscillation signal, wherein the first local oscillation signal is generated by a variable oscillator for a PLL frequency synthesizer, the second local oscillation signal is generated by a high frequency oscillator in which its oscillation frequency is controlled based on the frequency control signal generated by the modulator to perform the orthogonal demodulation processing, and the third local oscillation signal is generated by a fixed oscillator in which its oscillation frequency is fixed.

Abstract: Encoding data are given to a variable-length decoding circuit and are decoded, and are given to a memory so as to be stored therein. The same data are read out from the memory, whereby decoding processing of the encoding data is executed twice within one frame period. Decoding data due to the twice decoding processings are stored in the memory at an output part thereof. Data of odd fields are read out in display order in the first half of the display period of one frame. Data of even fields are read out in display order in the latter half of the display period of one frame. Thus, even in case where restored image data of a B-picture are outputted in interlacing, a memory capacity can be reduced.

Abstract: A read control circuit reads image data, which are stored in a decoding image memory, at a read speed m/n times a display speed. These image data are written to line memories by a write control circuit. A read-address control circuit reads the image data from the line memories at a display speed, and line data for a letter-box image are generated by multipliers and an adder. Specifically, the line data of m lines which are read from the decoding image memory are transformed to n lines so that a letter-box display is made possible. Thus, letter-box transformation processing is performed with less memory capacity without the use of a field memory.

Abstract: A variable length code recording/playback apparatus, which by encoding intra-frame data and inter-frame data in variable length code, records them as recorded codes on prescribed locations of tracks of a recording medium and plays them back, which includes a data rearranger for recording the data in areas to be played back at least two specific speed mode playbacks on the tracks by rearranging prescribed data out of the data encoded in variable length code, a variable length decoder for playing back the data recorded on the recording medium and decoding it in variable length code, a data restorer for controlling and restoring the time series of the output of the variable length decoder to the original data train before the rearrangement, and a decoder for constructing a playback picture from the decoded outputs for several frames in the specific speed mode playback by decoding the output of this data restorer.

Abstract: A variable length code recording/playback apparatus, which by encoding intra-frame data and inter-frame data in variable length code, records them as recorded codes on prescribed locations of tracks of a recording medium and plays them back, which includes a data rearranger for recording the data in areas to be played back at least two specific speed mode playbacks on the tracks by rearranging prescribed data out of the data encoded in variable length code, a variable length decoder for playing back the data recorded on the recording medium and decoding it in variable length code, a data restorer for controlling and restoring the time series of the output of the variable length decoder to the original data train before the rearrangement, and a decoder for constructing a playback picture from the decoded outputs for several frames in the specific speed mode playback by decoding the output of this data restorer.

Abstract: A recording/reproducing apparatus for a data packet stream having an extractor for extracting data packets of a selected type from an input packet train in which different types of data packets have been time-division multiplexed together. The apparatus also has a recording circuit for recording the extracted data packets, and a reproducing circuit for reproducing the recorded extracted data packets. A dummy packet producer, which produces dummy packets that correspond to data packets that have not been extracted, is also provided. Further, the apparatus has an output circuit that outputs an output data packet train. The output data packet train is produced by combining the reproduced extracted data packets and the dummy packets in accordance with the order in which the different types of data packets are positioned within the input packet train.

Abstract: A cooking apparatus such as a rice cooker includes means for obtaining a value or a combination of values indicative of an amount of food that is to be cooked, and a fuzzy inference section for operating on that value or combination of values to determine a level of heating power to be supplied to a heater element of the apparatus, during at least one part of the cooking process. The amount-indicating value can be obtained for example as a rate of change of temperature of the food while it is being heated to boiling point. The apparatus can further be configured to determine a plurality of cooking control parameters, by fuzzy inference operation, based on a specified degree of final hardness of the cooked food, which can be selectively inputted by the user.