Abstract: A circuit design support method includes obtaining shared circuit information indicating various types of shared circuits each executing at least any one of various types of logical computations and causing plural signal lines to share an observation point at which a signal value is observable; determining for each of the signal lines to be observed in a circuit under-design, a value based on controllability representing ease of control to set a value of the signal line to be a specific value; selecting based on the obtained shared circuit information, any one shared circuit among the various types of shared circuits; and generating correlation information that correlates each input terminal of the selected shared circuit with a signal line among the signal lines to be observed and whose value determined therefor is equal to a non-controlling value of a logical computation executed for an input signal input into the input terminal.

Abstract: Provided are: a programmable logic device capable of efficiently verifying whether an internal status of each sequential circuit makes transition equivalent to that of a logic program written in a hardware description language (HDL); and a verification method for the programmable logic device. A programmable logic device 10 includes: an I/O unit 17 that inputs and outputs digital signals to and from implemented logic elements and an outside; generation units 12 (12a, 12b, 12c, 12d) that acquire internal status signals of sequential circuits included in respective corresponding divided regions 11 (11a, 11b, 11c, 11d) to each of which a group of the logic elements is assigned, and generate status information 13 (13a, 13b, 13c, 13d) for each divided region 11 as a unit; and a selective output unit 14 that acquires the status information 13 from each divided region 11 and selectively outputs the status information 13 to the outside.

Abstract: A circuit design support method includes obtaining shared circuit information indicating various types of shared circuits each executing at least any one of various types of logical computations and causing plural signal lines to share an observation point at which a signal value is observable; determining for each of the signal lines to be observed in a circuit under-design, a value based on controllability representing ease of control to set a value of the signal line to be a specific value; selecting based on the obtained shared circuit information, any one shared circuit among the various types of shared circuits; and generating correlation information that correlates each input terminal of the selected shared circuit with a signal line among the signal lines to be observed and whose value determined therefor is equal to a non-controlling value of a logical computation executed for an input signal input into the input terminal.

Abstract: An electric circuit includes a delayed clock generation circuit to which a first clock is supplied and which is configured to generate a first delayed clock and a second delayed clock, the first delayed clock being the first clock delayed by a first delay amount, and the second delayed clock being the first clock delayed by a second delay amount different from the first delay amount, an OR gate configured to receive the first clock, the first delayed clock, and the second delayed clock as inputs and to output a second clock, and a scan circuit to which the second clock is supplied.

Abstract: An electric circuit includes a delayed clock generation circuit to which a first clock is supplied and which is configured to generate a first delayed clock and a second delayed clock, the first delayed clock being the first clock delayed by a first delay amount, and the second delayed clock being the first clock delayed by a second delay amount different from the first delay amount, an OR gate configured to receive the first clock, the first delayed clock, and the second delayed clock as inputs and to output a second clock, and a scan circuit to which the second clock is supplied.

Abstract: Logic circuitry has a test point to detect a signal about a delay fault propagating on a logic path between an input terminal and an output terminal, the test point being coupled to the logic path, wherein the test point includes a delay component to delay timing to detect the signal about a delay fault propagating on the logic path by predetermined time.

Abstract: A logic circuit includes a gated clock buffer including a control node, being set in either a first state or a second state in response to an input signal applied to the control node, outputting an input clock signal supplied as an output signal in the first state, and fixing an output signal to a constant value in the second state, a plurality of scan flip-flops receiving the output signal of the gated clock buffer, and included in at least part of a scan chain, and a combinational logic circuit coupled to at least one of the plurality of scan flip-flops.

Abstract: A logic circuit includes a gated clock buffer including a control node, being set in either a first state or a second state in response to an input signal applied to the control node, outputting an input clock signal supplied as an output signal in the first state, and fixing an output signal to a constant value in the second state, a plurality of scan flip-flops receiving the output signal of the gated clock buffer, and included in at least part of a scan chain, and a combinational logic circuit coupled to at least one of the plurality of scan flip-flops.

Abstract: A storing unit stores therein correspondence information between a pixel value of a pixel and a layout and pixel values of a plurality of pixels obtained by increasing a resolution of the pixel for each main scanning direction. A replacing unit replaces each pixel of image data input from an input unit with a layout and pixel values of a plurality of pixels based on the correspondence information for each main scanning direction. Each of a plurality of writing units having different main scanning directions performs a writing process using the layout and the pixel values of the pixels replaced by the replacing unit following each main scanning direction.

Abstract: Logic circuitry has a test point to detect a signal about a delay fault propagating on a logic path between an input terminal and an output terminal, the test point being coupled to the logic path, wherein the test point includes a delay component to delay timing to detect the signal about a delay fault propagating on the logic path by predetermined time.

Abstract: A circuit quality evaluation method obtains an indicator linked to the quality of a circuit by applying information representing a minimum delay margin of a path passing through an assumed fault site, a machine cycle, and a delay fault occurrence frequency. Further, the circuit quality evaluation method evaluates the quality of the circuit based on the indicator.

Abstract: A cover (1) for preventing water from entering a junction block (10) is rotatably held on a bracket (15) used to mount the junction block on a vehicle body. A connector (38) is fitted into a connector holder (20) in an upper surface (10a) of the junction block (10). However, a connector (39) cannot be fitted into a connector holder (23) provided in a side surface (10b) unless the cover (1) is rotated counterclockwise. This enables the upper surface (10a) of the junction block (10) to be covered for a water-entrance preventing purpose, and can prevent such an operation from being forgotten.

Abstract: A cover (1) for preventing water from entering a junction block (10) is rotatably held on a bracket (15) used to mount the junction block on a vehicle body. A connector (38) is fitted into a connector holder (20) in an upper surface (10a) of the junction block (10). However, a connector (39) cannot be fitted into a connector holder (23) provided in a side surface (10b) unless the cover (1) is rotated counterclockwise. This enables the upper surface (10a) of the junction block (10) to be covered for a water-entrance preventing purpose, and can prevent such an operation from being forgotten.

Abstract: There are provided a sandblasting apparatus and a method for processing a workpiece which has a first surface to be processed adjacent to a second surface not to be processed. The apparatus includes a masking device for masking the second surface and an abrasive blowing device for causing abrasive grains to impinge against the workpiece to process the first surface. The masking device includes a masking tape, an intermittent tape traveling device for causing the masking tape to travel to index a portion of the masking tape in the vicinity of the workpiece intermittently, and an urging device for bringing the portion of the masking tape into contact with the second surface of the workpiece to cover the same.

Abstract: There is disclosed a method of and an apparatus for performing, using a sandblasting, a processing such as a chamfering of a workpiece which has a surface to be processed and a surface not to be processed located adjacent to each other. The workpiece (W) held by a holder (2) on a turntable (1) is transferred to a processing station (P.sub.1) by the rotation of the turntable (1). An injection nozzle (3) or (4) is directed toward the surface to be processed (f.sub.1) of the workpiece (W), while a jet nozzle (5) is directed toward the surface not to be processed (f.sub.2). The jet nozzle (5) is supplied with fluid such as air, and the nozzle (3) or (4) is supplied with air containing abrasive grains. The fluid discharged from the jet nozzle (5) prevents the abrasive grains from impinging against the surface not to be processed (f.sub.2).

Abstract: A method and apparatus for sandblasting a workpiece. The workpiece is placed at a machining position. Air is sucked around the workpiece at the machining position in a first direction to produce air streams. During sucking, abrasive grains are blown against a face of the workpiece in a second direction for sandblasting the work, the second direction crossing the first direction at an angle .theta. smaller than 90.degree.. Abrasive grains blown against peripheries of the workpiece are larger in velocity than abrasive grains blown against a central portion of the workpiece.

Abstract: A method of feeding a work, in which a jig having an attitude controlling groove formed therein is prepared. A first work is controlled to assume a predetermined attitude by placing the work in the attitude controlling groove. The jig is conveyed to a first position so that the attitude controlling groove is located at a second position. Then, the first work is moved to a third position in the controlling groove and the first work at the third position is transferred to a processing device.