Abstract: After contact holes for the P- and N-type source or drain regions of P- and N-channel MOSFETs have been made at a common step, an N-type impurity is ion-implanted into at least the N-type source or drain regions through the contact holes. The N-type impurity is annealed to fornm an N-type region which is deeper than the N-type source or drain regions. During the annealing treatment, the N-type source or drain regions are covered with an insulating film.

Abstract: A semiconductor device having a CMIS structure for forming a static random access memory is disclosed which device can increase the packing density of the memory and reduce the stand-by power thereof. In this semiconductor device, a first MISFET of a first conductivity type is formed on and a substrate, a second MISFET of a second conductivity type is formed over the first MISFET with a first insulating film therebetween to form a stacked CMIS structure. The second MISFET is made up of a first conductive film, a second insulating film and a second conductive film, with the source, drain and channel regions of the second MISFET being formed in the first conductive film. A first resistive drain region is formed between the channel and drain regions of the first conductive film so that an impurity of the second conductivity type is contained in the first resistive drain region at a lower concentration than in the drain region, or the first resistive drain region is substantially undoped.

Abstract: A static RAM having first word lines each defined by extended gate electrodes of MISFETs constituting memory cells, and second word lines which are separate from the first word lines. The RAM has a wiring for supplying a fixed potential such as a ground potential to the memory cells, the wiring being formed from the same layer as that for forming the second word lines.

Abstract: A semiconductor device includes a first conductor layer into which is diffused an impurity for lowering the resistance, and a second conductor layer provided on the upper side of the first conductor layer through a stopper layer which suppresses the out-diffusion of the impurity. By virtue of the existence of the stopper layer, it is possible to inhibit the above-described impurity from being diffused into the second conductor layer. In SRAM, resistance variations between high-resistance elements which correspond to the second conductor layer can be suppressed, so that it is possible to prevent the lowering of the yield with respect to the electrical reliability. In SRAM, further, the resistance of the high-resistance elements is not lowered; therefore, it is possible to reduce the power consumption.

Abstract: A driving and driven wheel velocity are detected by wheel velocity sensors. A reference velocity is set on the basis of the driven wheel velocity. A slip value of the driving wheel on the basis of a difference between the driving wheel velocity and reference velocity. A target output torque of an engine is set in accordance with the slip value of the driving wheel. The target output torque is corrected in accordance with a lateral acceleration generated in a widthwise direction of the vehicle. An output of the engine is controlled to reach the corrected target output torque.

Abstract: Driving and driven wheel velocities of a vehicle are detected by wheel velocity sensors, and a change in driven wheel velocities as a function of time is detected to obtain a driven wheel acceleration by the vehicle acceleration calculating section. A reference target torque is calculated on the basis of the driven wheel acceleration. A slip value of the driving wheels is calculated on the basis of the driving and driven wheel velocities, and a correction torque corresponding to the slip value is calculated every predetermined sampling time at TSn calculating section and TPn calculating section. The correction torque is substracted from the reference target torque to obtain a target engine torque. An engine output is controlled to obtain the target engine torque.

Abstract: A first slip value detecting section detects slip values of the driving wheels on the basis of differences between the outputs from a selected driving wheel velocity and a reference velocity. And a second slip value detecting section detects slip values of the driving wheels on the basis of differences between the outputs from a driving wheel velocity detecting section and the reference velocity. And an engine output is controlled in accordance with the slip values detected by the first slip value detecting section. And braking force is controlled in accordance with the slip values detected by the second slip value detecting section.

Abstract: This invention has traction control means having slip detecting means for detecting slipping of driving wheels, in accordance with an output signal from the driving wheel velocity detecting means and an output signal from the vehicle body velocity detecting means, and output rate calculating means for generating first instruction A for controlling engine output, in order to immediately decrease a slip rate, based on a slip start signal from the slip detecting means and for, when the slip rate is decreased to a predetermined value, generating second instruction B for controlling the engine to provide an output according to friction coefficient .mu. between a road surface and wheels, and engine output control means for controlling engine output on the basis of the first and second instructions and vehicle operating conditions.

Abstract: The slip values DVR, DVL of the right and left driving wheels are respectively detected. The left braking control means control the left driving wheel in accordance with a correction slip value DVFL of the left driving wheel calculated by the following equation on the basis of the slip values DVL, DVR and the coefficient KB set by the coefficient setting means.DVFL=KB.multidot.DVL+(1-KB).multidot.DVRThe right braking control means control the right driving wheel in accordance with a correction slip value DVFR of the right driving wheel calculated by the following equation on the basis of the slip values DVR, DVL and the coefficent KB:DVFR=KB.multidot.DVR+(1-KB).multidot.DVL.

Abstract: A static RAM exhibiting a high reliability and suited to a higher density of integration is disclosed. In each memory cell of this static RAM, the cross coupling of a flip-flop circuit is made by gate electrodes of MISFETs constituting this flip-flop circuit. In addition, a source line is formed by the same step as that of a word line. A resistance value of a polycrystalline silicon layer which is a load resistor is changed in accordance with information to be stored. Furthermore, semiconductor regions for preventing soft errors attributed to alpha particles etc. are formed under the MISFETs constituting the flip-flop circuit, so that the channels are not adversely affected.

Abstract: An SRAM including a memory cell having a high-resistance load element. The load element is formed from a polysilicon film, and an impurity is introduced into a least a part of the polysilicon film for the purpose of increasing the threshold voltage of a parasitic MISFET formed using the load element as its channel region. Alternatively, the deposition of the polysilicon film is carried out at a relatively high temperature, thereby preventing any increase in the current flowing through the load element, and thus reducing the power dissipation in the SRAM.

Abstract: Multi-layer film including a silicon oxide film formed by the CVD method and a film having a gettering function is used as a layer insulation film in a semiconductor device having a resistance constituted by polycrystalline silicon, so that an impurity is not introduced into a resistance element formed in the (intrinsic) polycrystalline silicon, which is thereby stabilized, resulting in an improved characteristic of the semiconductor device. A third layer, of Spin on Glass, can be formed on the film having a gettering function so as to improve the flatness of the layer insulation film.

Abstract: A semiconductor device includes a first conductor layer into which is diffused an impurity for lowering the resistance, and a second conductor layer provided on the upper side of the first conductor layer through a stopper layer which suppresses out-diffusion of the impurity. By virtue of the existence of the stopper layer, it is possible to inhibit the above-described impurity from being diffused into the second conductor layer. In a SRAM, resistance variations between high-resistance elements which correspond to the second conductor layer can be suppressed, so that it is possible to prevent lowering of the yield with respect to the electrical reliability. In a SRAM, further, the resistance of the high-resistance elements is not lowered; therefore, it is possible to reduce the power consumption.

Abstract: A method of making a static random-access memory device or SRAM including a memory cell having a high-resistance load element. The load element is formed from a polysilicon film, and an impurity is introduced into at least a part of the polysilicon film for the purpose of increasing the threshold voltage of a parasitic MISFET formed using the load element as its channel region. Alternatively, the deposition of the polysilicon film is carried out at a relatively high temperature, thereby preventing any increase in the current flowing through the load element, and thus reducing the power dissipation in the SRAM.

Abstract: A CMOS IC is formed on a semiconductor crystalline surface having a plane azimuth (110) or (023), or of a plane azimuth close thereto (plane azimuth substantially in parallel with the above-mentioned planes), in order to increase the speed of operation.At low temperatures, dependency of the carrier mobility upon the plane azimuth becomes more conspicuous as shown in FIG. 1, and the difference of mobility is amplified depending upon the planes. Therefore, employment of the above-mentioned crystalline planes helps produce a great effect when the CMOS device is to be operated at low temperature (e.g., 100.degree. K. or lower), and helps operate the device at high speeds.

Abstract: After contact holes for the P- and N-type source or drain regions of P- and N-channel MOSFETs have been made at a common step, an N-type impurity is ion-implanted into at least the N-type source or drain regions through the contact holes. The N-type impurity is annealed to form an N-type region which is deeper than the N-type source or drain regions. During the annealing treatment, the N-type source or drain regions are covered with an insulating film.

Abstract: A process for producing semiconductor devices having excellent electric characteristics such as high threshold voltage Vth and small leakage current, maintaining high yields while preventing the occurrence of thermal etching at the time of heat-treatment to form a well diffusion layer in semiconductor devices such as CMOS IC's. Namely, a semiconductor wafer having a silicon dioxide film formed on the main surface thereof is heat-treated at a high temperature in an inert gas atmosphere. In this case, oxygen is contained in small amounts in the inert gas, so that pinholes formed in the silicon dioxide film are buried therein by the action of oxygen gas. Therefore, thermal etching is not generated by the high temperature inert gas, and the yields of semiconductor devices can be increased.

Abstract: Disclosed is a method of manufacturing a semiconductor device which includes MOSFETs of the two-channel conductivity types of P- and N-channel types on a single semiconductor substrate. According to the present invention, a first mask and a second mask are used. The first mask covers that surface part of the semiconductor substrate in which the P-channel type MOSFET is to be formed, and it serves as a mask when an N-type impurity is introduced into the semiconductor substrate. The first mask has a property and etching rate different from those of a film formed by the thermal oxidation of the semiconductor substrate surface. The second mask covers that surface part of the semiconductor substrate which has been formed with the N-channel type MOSFET, and it serves as a mask when a P-type impurity is introduced into the semiconductor substrate. The second mask is used as an inter-layer insulator film.

Abstract: A process for preparing a solid pigment dispersed composition which comprises subjecting a liquid composition comprising at least one ethylenically unsaturated polymerizable compound, at least one resin dissolved or dispersed therein and at least one pigment dispersed therein to suspension or bulk polymerization, if necessary, with previous color matching.