Abstract: A plating apparatus for forming a wiring pattern on a surface of a semiconductor wafer by causing a plating liquid into contact with the surface of the semiconductor wafer, comprises a storage tank storing and heating a plating liquid, a plating tank provided adjacent to the storage tank and having an opening formed in a wall at the side opposite to the side adjacent to the storage tank. The plating tank is supplied with the plating liquid from the storage tank, and the opening is configured to bring the surface of the semiconductor wafer into contact with the treatment liquid within the treatment tank. A holding mechanism is provided for holding the semiconductor wafer vertically and pushing the surface of the semiconductor wafer to the opening. With this arrangement, it is possible to prevent the unevenness of the plating which would otherwise have been caused by the bubbles generated in the process of the plating.

Abstract: A multi-level wiring structure interconnects circuit components of an integrated circuit fabricated on a semiconductor substrate, and comprises a lower wiring of noble metal covered with an inter-level insulating film, an upper wiring of noble metal extending over the inter-level insulating film, and an inter-level wiring implemented by a tube-shaped metal film filled with a piece of noble metal and passing through the inter-level insulating film for interconnecting the lower and upper wirings so that an electric signal is propagated at high speed without sacrifice of resistivity against migration phenomena.

Abstract: A semiconductor device includes a semiconductor layer, an insulating film, a polysilicon film, and a plurality of high-impurity concentration regions. The semiconductor layer has a first conductive region and a second conductive region of a conductivity type opposite to that of the first conductive region. The insulating film is formed on the semiconductor layer having a plurality of small windows on at least said first conductive region. The polysilicon film covers the insulating film and is in contact with the semiconductor layer through the small windows. The plurality of high-impurity concentration regions are formed corresponding to the small windows.

Abstract: A dielectric isolation region of a bipolar semiconductor device having a U-groove which is covered over the inner surface thereof with an insulating film, and is filled with polysilicon. The surface of the U-groove polysilicon is covered with a silicon nitride film deposited by CVD technique. This structure permits the earlier steps of forming the dielectric isolation region and also the later steps of forming semiconductor elements to be carried out without causing the surface of the U-groove polysilicon to suffer thermal oxidation.