Patents by Inventor Shuji Kodama

Shuji Kodama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080272461
    Abstract: There is provided a semiconductor device with a configuration in which a dummy silicide area 11 is provided in the vicinity of a non-silicide area 2 to easily capture residual refractory metals, resulting in an improved yield by preventing the trapping of residual refractory metals into a non-silicide area and thereby reducing a junction leakage within the non-silicide area.
    Type: Application
    Filed: June 26, 2008
    Publication date: November 6, 2008
    Inventors: Takeshi Kamino, Toshiaki Tsutsumi, Shuji Kodama, Takio Ohno
  • Patent number: 7408239
    Abstract: There is provided a semiconductor device with a configuration in which a dummy silicide area 11 is provided in the vicinity of a non-silicide area 2 to easily capture residual refractory metals, resulting in an improved yield by preventing the trapping of residual refractory metals into a non-silicide area and thereby reducing a junction leakage within the non-silicide area.
    Type: Grant
    Filed: January 9, 2007
    Date of Patent: August 5, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Takeshi Kamino, Toshiaki Tsutsumi, Shuji Kodama, Takio Ohno
  • Publication number: 20070114666
    Abstract: There is provided a semiconductor device with a configuration in which a dummy silicide area 11 is provided in the vicinity of a non-silicide area 2 to easily capture residual refractory metals, resulting in an improved yield by preventing the trapping of residual refractory metals into a non-silicide area and thereby reducing a junction leakage within the non-silicide area.
    Type: Application
    Filed: January 9, 2007
    Publication date: May 24, 2007
    Inventors: Takeshi Kamino, Toshiaki Tsutsumi, Shuji Kodama, Takio Ohno
  • Patent number: 7180153
    Abstract: There is provided a semiconductor device with a configuration in which a dummy silicide area 11 is provided in the vicinity of a non-silicide area 2 to easily capture residual refractory metals, resulting in an improved yield by preventing the trapping of residual refractory metals into a non-silicide area and thereby reducing a junction leakage within the non-silicide area.
    Type: Grant
    Filed: October 23, 2001
    Date of Patent: February 20, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Takeshi Kamino, Toshiaki Tsutsumi, Shuji Kodama, Takio Ohno
  • Publication number: 20030013025
    Abstract: The version management circuit comprises a plurality of mask revision state output circuits and an EXOR circuit. Each mask revision state output circuit selectively outputs a low or high logical level by changing only one mask. The EXOR circuit conducts an EXOR arithmetic operation to a level output from the mask revision state output circuits and outputs the result as a register value. Thus, the version management circuit can be changed and the version code can be rewritten by revising only one mask even if the mask is other than a mask related to a circuit required to be changed.
    Type: Application
    Filed: December 13, 2001
    Publication date: January 16, 2003
    Inventors: Hidekazu Tawara, Shuji Kodama
  • Publication number: 20020140097
    Abstract: There is provided a semiconductor device with a configuration in which a dummy silicide area 11 is provided in the vicinity of a non-silicide area 2 to easily capture residual refractory metals, resulting in an improved yield by preventing the trapping of residual refractory metals into a non-silicide area and thereby reducing a junction leakage within the non-silicide area.
    Type: Application
    Filed: October 23, 2001
    Publication date: October 3, 2002
    Inventors: Takeshi Kamino, Toshiaki Tsutsumi, Shuji Kodama, Takio Ohno
  • Patent number: 5874911
    Abstract: Analog-to-digital converting circuitry includes first and second analog-to-digital converting units. A converting start controlling circuit sends out converting start timing signals START1 and START2 which are out of phase with each other. When the first or second analog-to-digital converting unit receives the corresponding converting start timing signal START1 or START2 from the converting start controlling circuit, it samples and holds an analog value of an input signal, and then successively converts the analog value into an n-bit digital signal bit-by-bit and sends out the digital signal. An output selecting circuit outputs the digital signals from the first and second analog-to-digital converting units alternatingly.
    Type: Grant
    Filed: October 7, 1997
    Date of Patent: February 23, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Shuji Kodama
  • Patent number: 5834212
    Abstract: Anti-human stromelysin monoclonal antibodies reactive with latent and active forms of stromelysin without discrimination between the two, each being immunoreactive with only one of the antigenic determinants of human stromelysin, are provided. The use of a combination of two such monoclonal antibodies which specifically react with different antigenic determinants of human stromelysin renders it possible to accurately determine the amount of human stromelysin in human body fluids, and thus to carry out the diagnosis of rheumatoid arthritis.There are thus provided said monoclonal antibodies per se, a sandwich enzyme immunoassay for the determination of the amount of human stromelysin in human body fluid samples using a combination of two such monoclonal antibodies, and a method for the diagnosis of rheumatoid arthritis using said immunoassay.
    Type: Grant
    Filed: April 6, 1995
    Date of Patent: November 10, 1998
    Inventors: Yasunori Okada, Masayoshi Shinmei, Taro Hayakawa, Kazushi Iwata, Yumi Korin, Shuji Kodama, Shinichi Yoshida
  • Patent number: 5190861
    Abstract: A method for diagnosing rheumatoid arthritis, which is characterized by enzyme-immunologically measuring the amount of collagenase inhibitor present in sera, plasmas or synovial fluids by way of a sandwich assay wherein two different monoclonal antibodies which specifically bind to different antigenic determinants of the collagenase inhibitor are used, and comparing the measured amount with that for normal subjects.
    Type: Grant
    Filed: April 25, 1989
    Date of Patent: March 2, 1993
    Assignee: Fuji Yakuhin Kogyo Kabushiki Kaisha
    Inventors: Taro Hayakawa, Shuji Kodama, Kazushi Iwata, Junichi Kishi, Kyoko Yamashita, Hisashi Iwata
  • Patent number: 5175084
    Abstract: A method for diagnosing hepatic carcinoma, which is characterized by enzyme-immunologically measuring the amount of collagenase inhibitor present in sera, plasmas of synovial fluids by way of a sandwich assay wherein two different monoclonal antibodies which specifically bind to different antigenic determinants of the collagenase inhibitor are used, and comparing the measured amount with that for normal subjects.
    Type: Grant
    Filed: June 23, 1989
    Date of Patent: December 29, 1992
    Assignee: Fuji Yakuhin Kogyo Kabushiki Kaisha
    Inventors: Kyoichi Inoue, Takafumi Ichida, Miki Miyagiwa, Taro Hayakawa, Shuji Kodama, Kazushi Iwata