Patents by Inventor Shuji Matsuo

Shuji Matsuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240069457
    Abstract: The toner contains binder resin-containing toner particles and silica fine particle S1, wherein the weight-average particle diameter of the toner is 4.0-15.0 ?m, both inclusive, peaks originating with the silica fine particle S1 are observed in 29 Si-NMR measurement of the silica fine particle S1, and, in the spectrum obtained by 29Si CP/MAS NMR or 29Si DD/MAS NMR, the peak area of a peak corresponding to the D1 unit structure in the silica fine particle S1, the peak area of a peak corresponding to the D2 unit structure in the silica fine particle S1, and the peak area of a peak corresponding to the Q unit structure in the silica fine particle S1 satisfy a prescribed relationship.
    Type: Application
    Filed: October 25, 2023
    Publication date: February 29, 2024
    Inventors: RYUJI MURAYAMA, SHIN KITAMURA, TORU TAKAHASHI, DAISUKE TSUJIMOTO, RYUICHIRO MATSUO, HITOSHI SANO, NOBUYUKI FUJITA, SHUJI YAMADA, YUKA GUNJI, TAKAKUNI KOBORI, YOSHIHIRO OGAWA, ATSUHIKO OHMORI, HIROKI KAGAWA, KEISUKE ADACHI, TOMOKO SUGITA
  • Patent number: 10490445
    Abstract: When a void is caused in an interlayer insulating film on a semiconductor substrate, the invention prevents short circuit between two or more contact plugs that sandwich the void therebetween via a conductive film buried in the void at the time of formation of the contact plugs. An element isolation region having an upper surface lower than a main surface of the semiconductor substrate is formed inside a trench in the main surface of the semiconductor substrate, so that a void formed immediately above the semiconductor substrate in an active region and a void formed immediately above the element isolation region are divided from each other. In this manner, a conductive film is prevented from being buried in the second void.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: November 26, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takao Kamoshima, Kojiro Horita, Shuji Matsuo
  • Publication number: 20180090365
    Abstract: When a void is caused in an interlayer insulating film on a semiconductor substrate, the invention prevents short circuit between two or more contact plugs that sandwich the void therebetween via a conductive film buried in the void at the time of formation of the contact plugs. An element isolation region having an upper surface lower than a main surface of the semiconductor substrate is formed inside a trench in the main surface of the semiconductor substrate, so that a void formed immediately above the semiconductor substrate in an active region and a void formed immediately above the element isolation region are divided from each other. In this manner, a conductive film is prevented from being buried in the second void.
    Type: Application
    Filed: August 23, 2017
    Publication date: March 29, 2018
    Inventors: Takao KAMOSHIMA, Kojiro HORITA, Shuji MATSUO
  • Patent number: 8439508
    Abstract: A projector that projects an image on a screen, includes: plural image generating units that generate an image lights representing the image; a main body housing that houses the plural image generating units; and plural projection optical units that are provided in the main body housing to respectively correspond to the plural image generating units and project the image lights generated by the image generating units on the screen.
    Type: Grant
    Filed: November 20, 2009
    Date of Patent: May 14, 2013
    Assignee: Seiko Epson Corporation
    Inventors: Shuji Matsuo, Takeshi Ishikawa, Hirofumi Kasuga, Hiroshi Midorikawa, Masahiko Nunokawa
  • Publication number: 20110237036
    Abstract: By ion-implanting an inert gas, for example, nitrogen into a polycrystalline silicon film in an nMIS forming region from an upper surface of the polycrystalline silicon film down to a predetermined depth, an upper portion of the polycrystalline silicon film is converted to an amorphous form to form an amorphous/polycrystalline silicon film. And then, an n-type impurity, for example, phosphorous is ion-implanted into the amorphous/polycrystalline silicon film to form an n-type amorphous/polycrystalline silicon film, the n-type amorphous/polycrystalline silicon film is processed to form a gate electrode having a gate length shorter than 0.1 ?m, a sidewall formed of an insulating film is formed on a side wall of the gate electrode, and a source/drain diffusion layer is formed. Thereafter, a cobalt silicide (CoSi2) layer is formed on an upper portion of the gate electrode by salicide technique.
    Type: Application
    Filed: June 7, 2011
    Publication date: September 29, 2011
    Inventors: Hiroyuki OHARA, Shino TAKAHASHI, Kenji KANAMITSU, Shuji MATSUO
  • Publication number: 20100128228
    Abstract: A projector that projects an image on a screen, includes: plural image generating units that generate an image lights representing the image; a main body housing that houses the plural image generating units; and plural projection optical units that are provided in the main body housing to respectively correspond to the plural image generating units and project the image lights generated by the image generating units on the screen.
    Type: Application
    Filed: November 20, 2009
    Publication date: May 27, 2010
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Shuji MATSUO, Takeshi ISHIKAWA, Hirofumi KASUGA, Hiroshi MIDORIKAWA, Masahiko NUNOKAWA
  • Patent number: 7666728
    Abstract: A method of manufacture of a semiconductor device includes forming a gate insulating film and gate electrode made of polycrystalline silicon over a semiconductor substrate; implanting ions into the semiconductor substrate to form a semiconductor region as a source or drain; forming a cobalt film and a titanium nitride film over the semiconductor substrate to cover the gate electrode; carrying out annealing to cause a reaction between Co and Si and the semiconductor region to form a CoSi layer; carrying out wet cleaning to remove the titanium nitride film and unreacted cobalt film to leave the CoSi layer over the gate electrode and semiconductor region; carrying out annealing to cause a reaction between the CoSi layer and the gate electrode and semiconductor region to form a CoSi2 layer; carrying out HPM cleaning; and forming over the semiconductor substrate a silicon nitride film by low-pressure CVD to cover the gate electrode.
    Type: Grant
    Filed: February 8, 2008
    Date of Patent: February 23, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Shuji Matsuo, Katsuhiro Uchimura, Yasuko Yoshida, Kota Funayama, Yutaka Takeshima
  • Publication number: 20100019324
    Abstract: By ion-implanting an inert gas, for example, nitrogen into a polycrystalline silicon film in an nMIS forming region from an upper surface of the polycrystalline silicon film down to a predetermined depth, an upper portion of the polycrystalline silicon film is converted to an amorphous form to form an amorphous/polycrystalline silicon film. And then, an n-type impurity, for example, phosphorous is ion-implanted into the amorphous/polycrystalline silicon film to form an n-type amorphous/polycrystalline silicon film, the n-type amorphous/polycrystalline silicon film is processed to form a gate electrode having a gate length shorter than 0.1 ?m, a sidewall formed of an insulating film is formed on a side wall of the gate electrode, and a source/drain diffusion layer is formed. Thereafter, a cobalt silicide (CoSi2) layer is formed on an upper portion of the gate electrode by salicide technique.
    Type: Application
    Filed: December 22, 2006
    Publication date: January 28, 2010
    Inventors: Hiroyuki Ohara, Shino Takahashi, Kenji Kanamitsu, Shuji Matsuo
  • Publication number: 20080142901
    Abstract: A method of manufacture of a semiconductor device includes forming a gate insulating film and gate electrode made of polycrystalline silicon over a semiconductor substrate; implanting ions into the semiconductor substrate to form a semiconductor region as a source or drain; forming a cobalt film and a titanium nitride film over the semiconductor substrate to cover the gate electrode; carrying out annealing to cause a reaction between Co and Si and the semiconductor region to form a CoSi layer; carrying out wet cleaning to remove the titanium nitride film and unreacted cobalt film to leave the CoSi layer over the gate electrode and semiconductor region; carrying out annealing to cause a reaction between the CoSi layer and the gate electrode and semiconductor region to form a CoSi2 layer; carrying out HPM cleaning; and forming over the semiconductor substrate a silicon nitride film by low-pressure CVD to cover the gate electrode.
    Type: Application
    Filed: February 8, 2008
    Publication date: June 19, 2008
    Inventors: Shuji MATSUO, Katsuhiro Uchimura, Yasuko Yoshida, Kota Funayama, Yutaka Takeshima
  • Patent number: 7348230
    Abstract: A method of manufacture of a semiconductor device includes forming a gate insulating film and a gate electrode made of polycrystalline silicon over a semiconductor substrate; implanting ions into the semiconductor substrate to form a semiconductor region as a source or drain; forming a cobalt film and a titanium nitride film over the semiconductor substrate to cover the gate electrode; carrying out annealing to cause a reaction between Co and Si and the semiconductor region to form a CoSi layer; carrying out wet cleaning to remove the titanium nitride film and unreacted cobalt film to leave the CoSi layer over the gate electrode and semiconductor region; carrying out annealing to cause a reaction between the CoSi layer and the gate electrode and semiconductor region to form a CoSi2 layer; carrying out HPM cleaning; and forming over the semiconductor substrate a silicon nitride film by low-pressure CVD to cover the gate electrode.
    Type: Grant
    Filed: December 10, 2004
    Date of Patent: March 25, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Shuji Matsuo, Katsuhiro Uchimura, Yasuko Yoshida, Kota Funayama, Yutaka Takeshima
  • Publication number: 20070052095
    Abstract: Provided is a technology capable of improving the reliability of a semiconductor device using WPP by preventing a short-circuit failure between uppermost-level interconnects. In the present invention, a buffer layer is formed between an uppermost-level interconnect and redistribution interconnect. The uppermost-level interconnect is made of a copper film, while the buffer layer is made of an aluminum film. The redistribution interconnect is made of a film stack of a copper film and a nickel film. In such a semiconductor device, stress concentration occurs at a triple point when temperature cycling between low temperature and high temperature is performed. The stress concentration on the triple point is relaxed by the presence of the buffer layer, whereby the conduction of the stress to an interface just below the triple point can be suppressed. Peeling due to the stress at the interface can thus be prevented.
    Type: Application
    Filed: September 5, 2006
    Publication date: March 8, 2007
    Inventors: Katsuhiro Torii, Shuji Matsuo
  • Publication number: 20050145897
    Abstract: A method of manufacture of a semiconductor device includes forming a gate insulating film and a gate electrode made of polycrystalline silicon over a semiconductor substrate; implanting ions into the semiconductor substrate to form a semiconductor region as a source or drain; forming a cobalt film and a titanium nitride film over the semiconductor substrate to cover the gate electrode; carrying out annealing to cause a reaction between Co and Si and the semiconductor region to form a CoSi layer; carrying out wet cleaning to remove the titanium nitride film and unreacted cobalt film to leave the CoSi layer over the gate electrode and semiconductor region; carrying out annealing to cause a reaction between the CoSi layer and the gate electrode and semiconductor region to form a CoSi2 layer; carrying out HPM cleaning; and forming over the semiconductor substrate a silicon nitride film by low-pressure CVD to cover the gate electrode.
    Type: Application
    Filed: December 10, 2004
    Publication date: July 7, 2005
    Inventors: Shuji Matsuo, Katsuhiro Uchimura, Yasuko Yoshida, Kota Funayama, Yutaka Takeshima
  • Patent number: 5052832
    Abstract: A hand held printer for printing on a print paper when the printer is manually moved over the surface of the paper is provided, including a print mechanism supported within the housing to print inputted characters and drawings on the print paper upon manual manipulation of the housing. A thermal head is movably supported within the housing. A movement measurement unit indicates movement of the printer. A drive roller drives a ribbon take up roller and movement measurement unit. A clutch allows the drive roller to function only in a printing direction. A spring biases the drive roller towards an operating position, the drive roller moving to the print surface independently of the thermal head when the drive roller is biased by the spring.
    Type: Grant
    Filed: July 12, 1989
    Date of Patent: October 1, 1991
    Assignee: Seiko Epson Corporation
    Inventors: Takaaki Akiyama, Shuji Matsuo, Masahiro Fujii, Mitsukazu Kurose, Osamu Nakamura, Masahiro Kamijo
  • Patent number: 5020928
    Abstract: A hand held printer for printing on a print paper when the printer is manually moved over the surface of the paper is provided. A single manually manipulatable housing supports an input for imputting characters and drawings to be printed and a display for displaying the inputted characters and drawings. A print mechanism supported within the housing prints the inputted characters and drawings on the print paper upon manual manipulation of the housing. A thermal head is supported within the housing. A thermal transfer ribbon traces a path through the printer. A slide guide which is slidable relative to the print surface supports a slide means. The slide means guides the thermal transfer ribbon to come in contact with the print surface.
    Type: Grant
    Filed: November 22, 1989
    Date of Patent: June 4, 1991
    Assignee: Seiko Epson Corporation
    Inventors: Takaaki Akiyama, Shuji Matsuo, Masahiro Fujii, Mitsukazu Kurose, Osamu Nakamura, Masahiro Kamijo