Patents by Inventor Shuji Michinaka
Shuji Michinaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8155204Abstract: The image decoding apparatus and the image decoding method according to one aspect of the present invention have a configuration for storing an image decoded in the past as a reference picture into a frame memory, in a field structure in which top lines in the reference picture are stored in a top area and bottom lines in the reference picture are stored in a bottom area, in order to use a part of the image decoded in the past as a reference block in a picture being presently decoded; and selectively copying and storing an uppermost top line or an uppermost bottom line in the reference picture to areas on the uppermost top line and the uppermost bottom line in the reference picture in the top area and the bottom area in the frame memory, and selectively copying and storing a lowermost top line or a lowermost bottom line in the reference picture to areas under the lowermost top line and the lowermost bottom line in the reference picture in the top area and the bottom area in the frame memory.Type: GrantFiled: September 19, 2007Date of Patent: April 10, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Tatsuhiro Suzumura, Shuji Michinaka, Kiwamu Watanabe, Masashi Jobashi, Takaya Ogawa, Hiromitsu Nakayama, Satoshi Takekawa, Yoshinori Shigeta, Akihiro Oue
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Patent number: 8023565Abstract: A picture processing apparatus includes a decoder configured to decode encoded data to generate a decoded picture. A picture memory has a plurality of banks each containing a plurality of pages to which row addresses are assigned, and is configured to store the decoded picture. A bank selector is configured to divide the decoded picture into a plurality of blocks, and to select a page of a different bank as a write location for a block adjacent in at least one of either a horizontal direction or a vertical direction. A write controller is configured to write pixel data of pixels occupying even lines of each of the blocks, and pixel data of pixels occupying odd lines of each of the blocks in a column address direction of each of the page in an alternating manner.Type: GrantFiled: June 27, 2006Date of Patent: September 20, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Tatsuhiro Suzumura, Akihiro Oue, Kunihiko Yahagi, Shuji Michinaka, Satoshi Takekawa, Kiwamu Watanabe
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Patent number: 7602319Abstract: An image decoding apparatus having: a table selection controller configured to output a syntax selection signal which selects one of a prefix, a suffix, and a syntax; a variable length code decoding device configured to receive a bit stream, the syntax selection signal, and a suffix length, and, by using data contained in the bit stream and the suffix length, simultaneously decode the prefix and the suffix and output the result if the syntax selection signal selects the prefix 1 and the suffix, and decode the syntax and output the result if the syntax selection signal selects the syntax; a level formation device configured to receive the decoded prefix, the decoded suffix, and the decoded syntax, and form and output a level; and a suffix length updating device configured to receive the decoded prefix, the decoded suffix, and the decoded syntax, and update the suffix length.Type: GrantFiled: March 3, 2008Date of Patent: October 13, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Tatsuhiro Suzumura, Shuji Michinaka, Kiwamu Watanabe, Satoshi Takekawa, Masashi Jobashi, Hiromitsu Nakayama, Yoshinori Shigeta, Takaya Ogawa, Akihiro Oue
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Patent number: 7586426Abstract: An image coding apparatus includes a variable length coding section, an arithmetic coding section and a common buffer memory. The variable length coding section inputs image data and outputs a binarized code sequence applied with variable length coding. The arithmetic coding section applies arithmetic coding to the binarized code sequence outputted from the variable length coding section. The common buffer memory transmits and receives data between the variable length coding section and the arithmetic coding section.Type: GrantFiled: May 20, 2008Date of Patent: September 8, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Kiwamu Watanabe, Shuji Michinaka, Tatsuhiro Suzumura, Hiromitsu Nakayama, Yoshinori Shigeta, Satoshi Takekawa, Masashi Jobashi, Takaya Ogawa, Akihiro Oue
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Patent number: 7567189Abstract: When a combination between a plurality of FIFO memories and a variable length coding table is used, a load generated by an increase in number of FIFO memories serving as output destinations of a codeword length output from the variable length coding table when the codeword length is output is reduced.Type: GrantFiled: February 7, 2008Date of Patent: July 28, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Takaya Ogawa, Masashi Jobashi, Kiwamu Watanabe, Tatsuhiro Suzumura, Satoshi Takekawa, Hiromitsu Nakayama, Yoshinori Shigeta, Akihiro Oue, Shuji Michinaka
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Publication number: 20080291062Abstract: An image coding apparatus includes a variable length coding section, an arithmetic coding section and a common buffer memory. The variable length coding section inputs image data and outputs a binarized code sequence applied with variable length coding. The arithmetic coding section applies arithmetic coding to the binarized code sequence outputted from the variable length coding section. The common buffer memory transmits and receives data between the variable length coding section and the arithmetic coding section.Type: ApplicationFiled: May 20, 2008Publication date: November 27, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kiwamu Watanabe, Shuji Michinaka, Tatsuhiro Suzumura, Hiromitsu Nakayama, Yoshinori Shigeta, Satoshi Takekawa, Masashi Jobashi, Takaya Ogawa, Akihiro Oue
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Publication number: 20080238733Abstract: According to the present invention, there is provided an image decoding apparatus having: a table selection controller configured to output a syntax selection signal which selects one of a prefix level_prefix, a suffix level_suffix, and a TrailingOnes syntax; a variable-length code decoding device configured to receive a bit stream, the syntax selection signal, and a suffix length suffixLength, and, by using data contained in the bit stream and the suffix length suffixLength, simultaneously decode the prefix level_prefix and the suffix level_suffix and output the result if the syntax selection signal selects the prefix level_prefix and the suffix level_suffix, and decode the TrailingOnes syntax and output the result if the syntax selection signal selects the TrailingOnes syntax; a level formation device configured to receive the decoded prefix level_prefix, the decoded suffix level_suffix, and the decoded TrailingOnes syntax, and form and output a level; and a suffix length updating device configured to receiType: ApplicationFiled: March 3, 2008Publication date: October 2, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tatsuhiro SUZUMURA, Shuji Michinaka, Kiwamu Watanabe, Satoshi Takekawa, Masashi Jobashi, Hiromitsu Nakayama, Yoshinori Shigeta, Takaya Ogawa, Akihiro Oue
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Publication number: 20080198046Abstract: When a combination between a plurality of FIFO memories and a variable length coding table is used, a load generated by an increase in number of FIFO memories serving as output destinations of a codeword length output from the variable length coding table when the codeword length is output is reduced.Type: ApplicationFiled: February 7, 2008Publication date: August 21, 2008Applicant: Kabushiki Kaisha ToshibaInventors: Takaya OGAWA, Masashi Jobashi, Kiwamu Watanabe, Tatsuhiro Suzumura, Satoshi Takekawa, Hiromitsu Nakayama, Yoshinori Shigeta, Akihiro Oue, Shuji Michinaka
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Patent number: 7389007Abstract: A semiconductor memory apparatus according to the present invention includes: two bank areas each having one-port memories capable of performing writing and reading only with separate timings; a writing control circuit for writing data into said one-port memories in one bank area of the two bank areas; and a reading control circuit for reading data from said one-port memories of the other bank area and zero-clearing memory areas from which data has been read while the writing control circuit is writing data into the one bank area.Type: GrantFiled: March 27, 2006Date of Patent: June 17, 2008Assignee: Kabushiki Kaisha ToshibaInventor: Shuji Michinaka
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Publication number: 20080137754Abstract: The image decoding apparatus and the image decoding method according to one aspect of the present invention have a configuration for storing an image decoded in the past as a reference picture into a frame memory, in a field structure in which top lines in the reference picture are stored in a top area and bottom lines in the reference picture are stored in a bottom area, in order to use a part of the image decoded in the past as a reference block in a picture being presently decoded; and selectively copying and storing an uppermost top line or an uppermost bottom line in the reference picture to areas on the uppermost top line and the uppermost bottom line in the reference picture in the top area and the bottom area in the frame memory, and selectively copying and storing a lowermost top line or a lowermost bottom line in the reference picture to areas under the lowermost top line and the lowermost bottom line in the reference picture in the top area and the bottom area in the frame memory.Type: ApplicationFiled: September 19, 2007Publication date: June 12, 2008Applicant: Kabushiki Kaisha ToshibaInventors: Tatsuhiro SUZUMURA, Shuji Michinaka, Kiwamu Watanabe, Masashi Jobashi, Takaya Ogawa, Hiromitsu Nakayama, Satoshi Takekawa, Yoshinori Shigeta, Akihiro Oue
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Publication number: 20070147511Abstract: An image processing apparatus includes: a frame memory; a buffer memory that stores pixel values of macroblocks of a first region including a first macroblock; a deblocking filter unit that is operable to: (1) read out the pixel values of the first region from the buffer memory; (2) apply the deblocking filter to the first macroblock; and (3) store the pixel values back into the buffer memory; and a pixel transfer unit that is operable to: (4) transfer pixel values of a macroblock not included in a second region that includes a second macroblock to be processed next to the first macroblock, from the buffer memory to the frame memory; and (5) transfer pixel values of a macroblock included in the second region but not included in the first region, from the frame memory to the buffer memory.Type: ApplicationFiled: December 18, 2006Publication date: June 28, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Takaya Ogawa, Kiwamu Watanabe, Tatsuhiro Suzumura, Satoshi Takekawa, Hiromitsu Nakayama, Yoshinori Shigeta, Akihiro Oue, Shuji Michinaka
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Publication number: 20060291568Abstract: A picture processing apparatus includes a decoder configured to decode encoded data to generate a decoded picture. A picture memory has a plurality of banks each containing a plurality of pages to which row addresses are assigned, and is configured to store the decoded picture. A bank selector is configured to divide the decoded picture into a plurality of blocks, and to select a page of a different bank as a write location for a block adjacent in at least one of either a horizontal direction or a vertical direction. A write controller is configured to write pixel data of pixels occupying even lines of each of the blocks, and pixel data of pixels occupying odd lines of each of the blocks in a column address direction of each of the page in an alternating manner.Type: ApplicationFiled: June 27, 2006Publication date: December 28, 2006Applicant: Kabushiki Kaisha ToshibaInventors: Tatsuhiro Suzumura, Akihiro Oue, Kunihiko Yahagi, Shuji Michinaka, Satoshi Takekawa, Kiwamu Watanabe
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Publication number: 20060202874Abstract: A system for decoding a variable-length codeword includes a buffer circuit storing the codeword, a detection circuit detecting the number of bits of a prefix portion of the codeword by use of a detection table while updating the codeword, an extraction circuit extracting a codeword of a suffix portion of the codeword based on the number of bits of the prefix portion while updating the codeword, and a first decoding circuit decoding the codeword base on the number of bits of the prefix portion and the codeword of the suffix portion.Type: ApplicationFiled: June 27, 2005Publication date: September 14, 2006Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kiwamu Watanabe, Shuji Michinaka, Akihiro Oue, Tatsuhiro Suzumura, Satoshi Takekawa
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Patent number: 7102550Abstract: A system for decoding a variable-length codeword includes a buffer circuit storing the codeword, a detection circuit detecting the number of bits of a prefix portion of the codeword by use of a detection table while updating the codeword, an extraction circuit extracting a codeword of a suffix portion of the codeword based on the number of bits of the prefix portion while updating the codeword, and a first decoding circuit decoding the codeword base on the number of bits of the prefix portion and the codeword of the suffix portion.Type: GrantFiled: June 27, 2005Date of Patent: September 5, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Kiwamu Watanabe, Shuji Michinaka, Akihiro Oue, Tatsuhiro Suzumura, Satoshi Takekawa
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Publication number: 20060165299Abstract: A semiconductor memory apparatus according to the present invention includes: two bank areas each having one-port memories capable of performing writing and reading only with separate timings; a writing control circuit for writing data into said one-port memories in one bank area of the two bank areas; and a reading control circuit for reading data from said one-port memories of the other bank area and zero-clearing memory areas from which data has been read while the writing control circuit is writing data into the one bank area.Type: ApplicationFiled: March 27, 2006Publication date: July 27, 2006Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Shuji Michinaka
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Patent number: 7072530Abstract: A semiconductor memory apparatus according to the present invention includes: two bank areas each having one-port memories capable of performing writing and reading only with separate timings; a writing control circuit for writing data into said one-port memories in one bank area of the two bank areas; and a reading control circuit for reading data from said one-port memories of the other bank area and zero-clearing memory areas from which data has been read while the writing control circuit is writing data into the one bank area.Type: GrantFiled: September 26, 2001Date of Patent: July 4, 2006Assignee: Kabushiki Kaisha ToshibaInventor: Shuji Michinaka
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Publication number: 20060126743Abstract: The present invention provides a moving picture format variable length code (VLC) decoder that decodes at a high speed. The VLC decoder includes an input data memory, which is stored with a pixel data coefficient string in moving picture format, a table reference device, which is stored with table reference data and receives memory data from the input data memory, table storage memory including a reference table, which is stored with parametric data, receives table reference data ARG from the table reference device, and transmits parametric data to the table reference device, and output data memory, which receives reference table data made from a coefficient flag output from the table reference device and the last coefficient flag.Type: ApplicationFiled: May 12, 2005Publication date: June 15, 2006Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Satoshi Takekawa, Shuji Michinaka, Kiwamu Watanabe, Tatsuhiro Suzumura, Akihiro Oue
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Publication number: 20020036937Abstract: A semiconductor memory apparatus according to the present invention includes: two bank areas each having one-port memories capable of performing writing and reading only with separate timings; a writing control circuit for writing data into said one-port memories in one bank area of the two bank areas; and a reading control circuit for reading data from said one-port memories of the other bank area and zero-clearing memory areas from which data has been read while the writing control circuit is writing data into the one bank area.Type: ApplicationFiled: September 26, 2001Publication date: March 28, 2002Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Shuji Michinaka