Patents by Inventor Shuji Miyashita

Shuji Miyashita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5737200
    Abstract: Semiconductor devices operating as switching elements for a power converter are protected in the invention. Each pair has upper and lower arms and is connected in series between electrodes of a DC power supply. In the converter, the pairs of the semiconductor devices are switched to convert power from the DC power supply to obtain converted power from a connection between the semiconductor devices in each pair. In the method, magnitudes of drive signals or drive-circuit constants for the semiconductor devices of the upper and lower arms in each pair are set to be different from each other, and a protection device is provided in only one of the semiconductor devices in the pair of the upper and lower arms. The protection device monitors voltage between main terminals of the semiconductor device where the protection device is installed, and controls the drive signal for the semiconductor device to prevent passage of an excessive current therethrough.
    Type: Grant
    Filed: January 3, 1997
    Date of Patent: April 7, 1998
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Shuji Miyashita, Ayumi Fujibayashi
  • Patent number: 5430326
    Abstract: A semiconductor device includes at least one semiconductor element contained in a casing, with main terminals and auxiliary terminals drawn from the semiconductor electrodes disposed on the upper face of the casing. The main terminals and the auxiliary terminals are arranged on the same plane at the same height without disposing partitions between the terminals so that the devices can be mounted on a printed wiring board on which the necessary conductor patterns for the main circuit have already been formed. In an alternative embodiment, the main terminals are arranged at a level slightly higher than the auxiliary terminals with the auxiliary terminals being surrounded by a supporting guide.
    Type: Grant
    Filed: May 5, 1994
    Date of Patent: July 4, 1995
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Shuji Miyashita
  • Patent number: 5361189
    Abstract: A semiconductor device 1 having external lead terminals 14 and 15 on an upper level surface portion 12 and a lower level surface portion 13 formed in a top cover 11 of a resin package so as to produce a level difference between them in combination with an external lead terminal adaptor 2 having terminal conductors 22 on a terminal block body 21 adapted to be stacked on the lower level surface portion so that the level difference between the higher and lower level portions is compensated, and the terminal conductors of the adaptor are connected with the external lead terminals disposed on the lower level portion of the semiconductor device. This enables the terminal conductors and external lead terminals to have the same level or to be aligned in the same plane, so that external wiring between the semiconductor device and the printed circuit board mounted thereon can be easily accomplished.
    Type: Grant
    Filed: November 2, 1992
    Date of Patent: November 1, 1994
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Shuji Miyashita
  • Patent number: 5306949
    Abstract: In an external lead terminal 5 of a transistor module, an intermediate terminal portion 6 and an external lead terminal 8 are conductively connected to each other via a U-shaped intermediate terminal portion 7 having a curved portion 7b. Connected in parallel with this intermediate terminal portion 7 is a shortcircuit wire 9 having a larger electric resistance and a smaller inductance than the same. For this reason, even if a current is reduced suddenly in a state in which the current is flowing from the external terminal portion 8 to the intermediate terminal portion 6 via the intermediate terminal portion 7, the current shifts to the shortcircuit wire 9 side, so that a transient voltage is low. Consequently, it is provided a transistor module capable of reducing a transient voltage without being subjected to restrictions in the size of an external lead terminal while maintaining a high level of reliability.
    Type: Grant
    Filed: November 9, 1992
    Date of Patent: April 26, 1994
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Toshifusa Yamada, Shuji Miyashita, Toshihisa Shimizu