Patents by Inventor Shuji Murai

Shuji Murai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8237649
    Abstract: A liquid crystal driving device includes, for each of a plurality of scanning lines, a level shift and output buffer circuit including a first PMOSFET and a first NMOSFET connected in series, a second PMOSFET and a second NMOSFET connected in series, and CMOS inverter circuit. A gate of the first PMOSFET and a gate of the second NMOSFET may be connected to respective bias voltages. Alternatively, a gate of the first NMOSFET and a gate of the second PMOSFET may be connected to respective bias voltages. Each level shift and output buffer circuit receives a binary input signal and outputs a buffered signal having both levels shifted with respect to the input signal using six transistors.
    Type: Grant
    Filed: March 11, 2009
    Date of Patent: August 7, 2012
    Assignees: Semiconductor Components Industries, LLC, Sanyo Semiconductor Co., Ltd.
    Inventor: Shuji Murai
  • Publication number: 20090231258
    Abstract: A liquid crystal driving device comprising: a scanning line driving circuit including, for each of scanning lines, a first series circuit having a 1st-PMOSFET/1st-NMOSFET connected in series, both ends thereof connected respectively to points of 1st-potential/2nd-potential, configured to receive at a 1st-PMOSFET's gate a binary signal having two levels not higher than 1st-potential's level and higher than 2nd-potential's level, a second series circuit having a 2nd-PMOSFET/2nd-NMOSFET connected in series, both ends thereof connected respectively to points of 3rd-potential (>1st-potential)/2nd-potential, a 2nd-NMOSFET's gate connected to a connection point of the 1st-PMOSFET/1st-NMOSFET, and an output buffer circuit configured to buffer and output a voltage of a connection point of the 2nd-PMOSFET/2nd-NMOSFET, a 1st-NMOSFET's gate applied with a 1st-bias-voltage adapted such that the 2nd-NMOSFET is turned ON-or-OFF in response to the binary signal's level, a 2nd-PMOSFET's gate applied with a 2nd-bias-voltage
    Type: Application
    Filed: March 11, 2009
    Publication date: September 17, 2009
    Applicants: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.
    Inventor: Shuji Murai
  • Patent number: 5350547
    Abstract: An expert system for retrieving molding conditions, in which a statistical technique is added to the functions of the conventional expert system, causes of defects are inferred from the records of countermeasures taken and inputted defect occurrence situation, conditions for temporary molding are obtained while repeating test molding, qualitative defects are extracted from defects occurred, a boundary of a region in which defects occur is determined with decision analysis of qualitative defects extracted with the use of the record of countermeasures as above, a condition for molding to eliminate the qualitative defects is determined on the basis of the boundary of region of defects occurrence, quantitative defects are extracted from defects occurred, and molding conditions for eliminating the quantitative defects are determined by performing analysis of variance depending on design of experiment with the quantitative defects extracted from the record of countermeasures, whereby the frequency of experiment is
    Type: Grant
    Filed: November 30, 1992
    Date of Patent: September 27, 1994
    Assignee: Kabushiki Kaisha Komatsu Seisakusho
    Inventors: Hiroyoshi Yamaguchi, Shuji Murai, Tatsuo Mimura
  • Patent number: 5195029
    Abstract: A control apparatus having an inference function includes an input unit for inputting situations of problems in a product and a storage unit storing the situations of the problems in the product, causes corresponding to respective situations of the problems and countermeasure plans corresponding to the respective causes, and infers countermeasure plans which are most suitable according to contents stored in the storage unit and the situations of the problems input by the input unit. The apparatus displays countermeasure plans in the course of inference on a display unit during the process of inference, performs the control of an injection machine according to a countermeasure plan when the countermeasure plan has been selected from among the countermeasure plans displayed, and performs the control of the injection machine according to the most suitable countermeasure plan inferred by the inference function when a countermeasure plan has not been selected.
    Type: Grant
    Filed: January 16, 1990
    Date of Patent: March 16, 1993
    Assignee: Kabushiki Kaisha Komatsu Seisakusho
    Inventors: Shuji Murai, Hiroyoshi Yamaguchi, Naoto Otsuka