Patents by Inventor Shuji Nomura

Shuji Nomura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8900426
    Abstract: A sputtering apparatus including a target holder configured to hold at least two targets; a substrate holder configured to hold a substrate; a first shutter plate arranged between the target holder and the substrate holder, the first shutter plate having at least two holes and being capable of rotating around an axis; a second shutter plate arranged between the first shutter plate and the substrate holder, the second shutter plate having at least two holes and being capable of rotating around the axis; wherein the first and second shutter plates are rotated such that paths are simultaneously created between the at least two targets and the substrate through the at least two holes of the rotated first shutter plate and the at least two holes of the rotated second shutter plate, and a film is formed on the substrate by co-sputtering of the at least two targets.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: December 2, 2014
    Assignee: Canon Anelva Corporation
    Inventors: Shuji Nomura, Ayumu Miyoshi, Hiroshi Miki
  • Publication number: 20120097533
    Abstract: A sputtering apparatus including a target holder configured to hold at least two targets; a substrate holder configured to hold a substrate; a first shutter plate arranged between the target holder and the substrate holder, the first shutter plate having at least two holes and being capable of rotating around an axis; a second shutter plate arranged between the first shutter plate and the substrate holder, the second shutter plate having at least two holes and being capable of rotating around the axis; wherein the first and second shutter plates are rotated such that paths are simultaneously created between the at least two targets and the substrate through the at least two holes of the rotated first shutter plate and the at least two holes of the rotated second shutter plate, and a film is formed on the substrate by co-sputtering of the at least two targets.
    Type: Application
    Filed: December 12, 2011
    Publication date: April 26, 2012
    Applicant: CANON ANELVA CORPORATION
    Inventors: Shuji NOMURA, Ayumu Miyoshi, Hiroshi Miki
  • Patent number: 7850827
    Abstract: A double-layer shutter control method of a multi-sputtering system provided with three targets in a single chamber and a double-layer rotating shutter mechanism having shutter plates which independently rotate and have holes formed therein, comprising selecting a target by a combination of holes of a first shutter plate and a second shutter plate and uses the selected target for a pre-sputtering step and a main sputtering step with continuous discharge so as to deposit a film on a substrate, whereby it is possible to prevent cross-contamination between targets due to target substances etc. deposited on the shutter plates.
    Type: Grant
    Filed: March 14, 2005
    Date of Patent: December 14, 2010
    Assignee: Canon Anelva Corporation
    Inventors: Shuji Nomura, Ayumu Miyoshi, Hiroshi Miki
  • Patent number: 7704556
    Abstract: The silicon nitride film forming method deposits a silicon nitride film on the substrate surface by maintaining the heating element at a predetermined temperature and by decomposing and/or activating a raw material gas supplied from the gas supply system.
    Type: Grant
    Filed: June 18, 2007
    Date of Patent: April 27, 2010
    Assignee: Canon Anelva Corporation
    Inventors: Hitoshi Morisaki, Yasushi Kamiya, Shuji Nomura, Masahiro Totuka, Tomoki Oku, Ryo Hattori
  • Publication number: 20090139865
    Abstract: A double-layer shutter control method of a multi-sputtering system provided with three targets in a single chamber and a double-layer rotating shutter mechanism having shutter plates which independently rotate and have holes formed therein, comprising selecting a target by a combination of holes of a first shutter plate and a second shutter plate and uses the selected target for a pre-sputtering step and a main sputtering step with continuous discharge so as to deposit a film on a substrate, whereby it is possible to prevent cross-contamination between targets due to target substances etc. deposited on the shutter plates.
    Type: Application
    Filed: November 17, 2008
    Publication date: June 4, 2009
    Applicant: Canon Anelva Corporation
    Inventors: Shuji Nomura, Ayumu Miyoshi, Hiroshi Miki
  • Publication number: 20080020140
    Abstract: A silicon nitride film forming method makes possible the high reproducibility of film quality or film thickness. The silicon nitride film forming method deposits a silicon nitride film on the substrate surface by maintaining the heating element at a predetermined temperature and by decomposing and/or activating a raw material gas supplied from the gas supply system.
    Type: Application
    Filed: June 18, 2007
    Publication date: January 24, 2008
    Inventors: Hitoshi Morisaki, Yasushi Kamiya, Shuji Nomura, Masahiro Totuka, Tomoki Oku, Ryo Hattori
  • Publication number: 20050199490
    Abstract: A double-layer shutter control method of a multi-sputtering system provided with three targets in a single chamber and a double-layer rotating shutter mechanism having shutter plates which independently rotate and have holes formed therein, comprising selecting a target by a combination of holes of a first shutter plate and a second shutter plate and uses the selected target for a pre-sputtering step and a main sputtering step with continuous discharge so as to deposit a film on a substrate, whereby it is possible to prevent cross-contamination between targets due to target substances etc. deposited on the shutter plates.
    Type: Application
    Filed: March 14, 2005
    Publication date: September 15, 2005
    Applicant: ANELVA Corporation
    Inventors: Shuji Nomura, Ayumu Miyoshi, Hiroshi Miki
  • Patent number: 6723664
    Abstract: This invention discloses a method and apparatus where a pre-treatment which reduce interfacial level density is carried out before thin film deposition on a substrate utilizing a catalytic gas phase reaction. The catalytic gas phase reaction is generated with a treatment gas which is supplied with the substrate via a thermal catalysis body provided near the substrate surface. Thin film deposition on the substrate surface is carried out after this pre-treatment. The thermal catalysis body is made of tungsten, molybdenum, tantalum, titanium or vanadium, and is heated by a heater. And, this invention also discloses a semiconductor device having a semiconductor-insulator junction with its interfacial level density is 1012 eV −1cm−2 or less, which is brought by the above pre-treatment in the insulator film deposition process.
    Type: Grant
    Filed: January 10, 2002
    Date of Patent: April 20, 2004
    Assignees: NEC Compound Semiconductor Devices, Ltd., Anelva Corporation
    Inventors: Hideki Matsumura, Akira Izumi, Atsushi Masuda, Yasunobu Nashimoto, Yosuke Miyoshi, Shuji Nomura, Kazuo Sakurai, Shouichi Aoshima
  • Patent number: 6699592
    Abstract: The invention provides a galvannealed steel sheet which has an oxide layer having 10 nm or larger thickness on the plateau of the coating layer flattened by temper rolling. With the use of the galvannealed steel sheet, no powdering occurs during press-forming, and stable and excellent sliding performance is attained. By selecting the area percentage of the plateau of the flattened coating layer to a range from 20 to 80%, making the coating layer single layer of &dgr;1 phase, and letting &zgr; phase exist in the &dgr;1 phase, further improved sliding performance and anti-powdering property are obtained.
    Type: Grant
    Filed: October 21, 2002
    Date of Patent: March 2, 2004
    Assignee: NKK Corporation
    Inventors: Shoichiro Taira, Yoshiharu Sugimoto, Junichi Inagaki, Toru Imokawa, Shuji Nomura, Michitaka Sakurai, Masaaki Yamashita, Kaoru Sato, Masayasu Nagoshi, Akira Gamou, Yoichi Miyakawa, Shunsaku Node, Masahiro Iwabuchi
  • Patent number: 6641703
    Abstract: A magnetic multi-layer film manufacturing apparatus has a transferring chamber, a plurality of film-depositing chambers, and a robotic transferring device. Each film-depositing chamber has a rotatable substrate holder, a plurality of targets positioned at an incline on an opposing interior surface from the substrate holder, and a double layer rotating shutter mechanism and is controllable to deposit at least one layer of a magnetic multi-layer film structure. Magnetic multi-layer film structures are formed by depositing a plurality of magnetic films divided into a plurality of groups, each one of the plurality of groups deposited in an associated one of the plurality of film-depositing chambers continuously in a laminated state. A first division between successive groups of magnetic films is between a metal oxide film and a magnetic layer continuous therewith and a second division is between an antiferromagnetic layer and a magnetic layer continuous therewith.
    Type: Grant
    Filed: November 30, 2001
    Date of Patent: November 4, 2003
    Assignee: Anelva Corporation
    Inventors: Shuji Nomura, Ayumu Miyoshi, Koji Tsunekawa
  • Publication number: 20030198743
    Abstract: The present invention is to provide a silicon nitride film forming apparatus and a forming method which makes possible the high reproducibility of film quality or film thickness. The silicon nitride film forming apparatus and forming method in which a heating element and a substrate are arranged in a vacuum vessel connected to a gas exhaust system and a gas supply system to deposit a silicon nitride film on the substrate surface by maintaining the heating element at a predetermined temperature and by decomposing and/or activating a raw material gas supplied from the gas supply system, comprises: an inner wall which is arranged in the vacuum vessel surrounding the heating element and the substrate so as to form a film formation space, a gas introduction means to introduce the raw material gas to the film forming space, and at least one of a heating means and a cooling means of the inner wall arranged to control the inner wall to a predetermined temperature.
    Type: Application
    Filed: April 22, 2003
    Publication date: October 23, 2003
    Inventors: Hitoshi Morisaki, Yasushi Kamiya, Shuji Nomura, Masahiro Totuka, Tomoki Oku, Ryo Hattori
  • Publication number: 20030175548
    Abstract: The invention provides a galvannealed steel sheet which has an oxide layer having 10 nm or larger thickness on the plateau of the coating layer flattened by temper rolling. With the use of the galvannealed steel sheet, no powdering occurs during press-forming, and stable and excellent sliding performance is attained. By selecting the area percentage of the plateau of the flattened coating layer to a range from 20 to 80%, making the coating layer single layer of &dgr;1 phase, and letting &zgr; phase exist in the &dgr;1 phase, further improved sliding performance and anti-powdering property are obtained.
    Type: Application
    Filed: October 21, 2002
    Publication date: September 18, 2003
    Inventors: Shoichiro Taira, Yoshiharu Sugimoto, Junichi Inagaki, Tomoko Inagaki, Toru Imokawa, Shuji Nomura, Michitaka Sakurai, Masaaki Yamashita, Kaoru Sato, Masayasu Nagoshi, Akira Gamou, Yoichi Miyakawa, Shunsaku Node, Masahiro Iwabuchi
  • Publication number: 20020086557
    Abstract: This invention discloses a method and apparatus where a pre-treatment which reduce interfacial level density is carried out before thin film deposition on a substrate utilizing a catalytic gas phase reaction. The catalytic gas phase reaction is generated with a treatment gas which is supplied with the substrate via a thermal catalysis body provided near the substrate surface. Thin film deposition on the substrate surface is carried out after this pre-treatment. The thermal catalysis body is made of tungsten, molybdenum, tantalum, titanium or vanadium, and is heated by a heater. And, this invention also discloses a semiconductor device having a semiconductor-insulator junction with its interfacial level density is 1012 eV −1cm−2 or less, which is brought by the above pre-treatment in the insulator film deposition process.
    Type: Application
    Filed: January 10, 2002
    Publication date: July 4, 2002
    Inventors: Hideki Matsumura, Akira Izumi, Atsushi Masuda, Yasunobu Nashimoto, Yosuke Miyoshi, Shuji Nomura, Kazuo Sakurai, Shouichi Aoshima
  • Publication number: 20020064595
    Abstract: A magnetic multi-layer film manufacturing apparatus has a transferring chamber, a plurality of film-depositing chambers, and a robotic transferring device. Each film-depositing chamber has a rotatable substrate holder, a plurality of targets positioned at an incline on an opposing interior surface from the substrate holder, and a double layer rotating shutter mechanism and is controllable to deposit at least one layer of a magnetic multi-layer film structure. Magnetic multi-layer film structures are formed by depositing a plurality of magnetic films divided into a plurality of groups, each one of the plurality of groups deposited in an associated one of the plurality of film-depositing chambers continuously in a laminated state. A first division between successive groups of magnetic films is between a metal oxide film and a magnetic layer continuous therewith and a second division is between an antiferromagnetic layer and a magnetic layer continuous therewith.
    Type: Application
    Filed: November 30, 2001
    Publication date: May 30, 2002
    Inventors: Shuji Nomura, Ayumu Miyoshi, Koji Tsunekawa
  • Patent number: 6349669
    Abstract: This invention discloses a method and apparatus where a pre-treatment which reduce interfacial level density is carried out before thin film deposition on a substrate utilizing a catalytic gas phase reaction. The catalytic gas phase reaction is generated with a treatment gas which is supplied with the substrate via a thermal catalysis body provided near the substrate surface. Thin film deposition on the substrate surface is carried out after this pre-treatment. The thermal catalysis body is made of tungsten, molybdenum, tantalum, titanium or vanadium, and is heated by a heater. And, this invention also discloses a semiconductor device having a semiconductor-insulator junction with its interfacial level density is 1012 eV−1 cm−2 or less, which is brought by the above pre-treatment in the insulator film deposition process.
    Type: Grant
    Filed: June 23, 1998
    Date of Patent: February 26, 2002
    Assignees: NEC Corporation, Anelva Corporation
    Inventors: Hideki Matsumura, Akira Izumi, Atsushi Masuda, Yasunobu Nashimoto, Yosuke Miyoshi, Shuji Nomura, Kazuo Sakurai, Shouichi Aoshima
  • Patent number: 6069094
    Abstract: This invention discloses a method and apparatus where a pre-treatment which reduce interfacial level density is carried out before thin film deposition on a substrate utilizing a catalytic gas phase reaction. The catalytic gas phase reaction is generated with a treatment gas which is supplied with the substrate via a thermal catalysis body provided near the substrate surface. Thin film deposition on the substrate surface is carried out after this pre-treatment. The thermal catalysis body is made of tungsten, molybdenum, tantalum, titanium or vanadium, and is heated by a heater. And, this invention also discloses a semiconductor device having a semiconductor-insulator junction with its interfacial level density is 10.sup.12 eV .sup.-1 cm.sup.-2 or less, which is brought by the above pre-treatment in the insulator film deposition process.
    Type: Grant
    Filed: September 5, 1997
    Date of Patent: May 30, 2000
    Assignees: Hideki Matsumra, NEC Corporation, ANELVA Corporation
    Inventors: Hideki Matsumura, Akira Izumi, Atsushi Masuda, Yasunobu Nashimoto, Yosuke Miyoshi, Shuji Nomura, Kazuo Sakurai, Shouichi Aoshima
  • Patent number: 5923089
    Abstract: A method and resulting structure for fabricating interconnects through an integrated circuit. The method includes adding more power lines 80, 100, 151 and/or increasing the width of power lines 120 and/or adding a power bus 140 near regions of high current flow. The resulting structure also provides more metallization near regions of high current flow. Similar to the method, the resulting structure may include additional power lines 80, 100, 151 and/or wider power lines 120 and/or a power bus 140 to increase the amount of metallization. An improved routing technique is also provided. Such routing technique includes providing an initial Ucs value and then adding additional lines near high current regions to decrease the Ucs value.
    Type: Grant
    Filed: March 10, 1997
    Date of Patent: July 13, 1999
    Assignee: Oki America, Inc.
    Inventors: Chingchi Yao, Ichiro Yamamoto, Shuji Nomura
  • Patent number: 5849423
    Abstract: A method for manufacturing a zinciferous plated steel sheet, comprises: forming a zinciferous plating layer on a steel sheet; and forming an Fe--Ni--O film on the zinciferous plating layer. The Fe--Ni--O film is formed by carrying out electrolysis with the steel sheet as a cathode in an aqueous solution, dipping the steel sheet in an aqueous solution, or spraying a mist on a surface of the zinciferous plating layer.
    Type: Grant
    Filed: November 18, 1996
    Date of Patent: December 15, 1998
    Assignee: NKK Corporation
    Inventors: Takayuki Urakawa, Toru Imokawa, Michitaka Sakurai, Jun-ichi Inagaki, Masaaki Yamashita, Shuji Nomura
  • Patent number: 5767011
    Abstract: A method and resulting structure for fabricating interconnects through an integrated circuit. The method includes adding more power lines 80, 100, 151 and/or increasing the width of power lines 120 and/or adding a power bus 140 near regions of high current flow. The resulting structure also provides more metallization near regions of high current flow. Similar to the method, the resulting structure may include additional power lines 80, 100, 151 and/or wider power lines 120 and/or a power bus 140 to increase the amount of metallization. An improved routing technique is also provided. Such routing technique includes providing an initial Ucs value and then adding additional lines near high current regions to decrease the Ucs value.
    Type: Grant
    Filed: November 14, 1996
    Date of Patent: June 16, 1998
    Assignee: Oki Semiconductor, an Operating Group of Oki America, Inc. or Oki America, Inc.
    Inventors: Chingchi Yao, Ichiro Yamamoto, Shuji Nomura