Abstract: To provide new instruction and device suitable for tracing execution of a computer program. In an embodiment, a CPU is configured so as to supply a constant to a trace unit in response to decoding of a first instruction having an immediate field indicating the constant. In addition, the trace unit is configured so as to output trace data including the constant in response to execution of the first instruction in the CPU.

Abstract: To provide new instruction and device suitable for tracing execution of a computer program. In an embodiment, a CPU is configured so as to supply a constant to a trace unit in response to decoding of a first instruction having an immediate field indicating the constant. In addition, the trace unit is configured so as to output trace data including the constant in response to execution of the first instruction in the CPU.

Abstract: A trace controller receives data access information during load instruction execution and ID (AID) of a load/store buffer to store the data access information during load instruction execution. Then, it generates trace control information TC based on the received data access information and selects a buffer to store the generated trace control information from a plurality of trace control buffers according to the received AID. After that, it receives read data information after load instruction execution and ID (RID) of a load/store buffer used for load instruction execution. Finally, it selects a buffer storing the trace control information TC from the plurality of trace control buffers according to the RID.

Abstract: A trace controller receives data access information during load instruction execution and ID (AID) of a load/store buffer to store the data access information during load instruction execution. Then, it generates trace control information TC based on the received data access information and selects a buffer to store the generated trace control information from a plurality of trace control buffers according to the received AID. After that, it receives read data information after load instruction execution and ID (RID) of a load/store buffer used for load instruction execution. Finally, it selects a buffer storing the trace control information TC from the plurality of trace control buffers according to the RID.

Abstract: A computer system operates for pipe-line processing, and includes a cache memory and a tracing circuit for tracing the operation of the pipe-line processor for developing the computer system. The pipe-line processing is executed in separate stage blocks, and the trace data are supplied to the tracing circuit through a dedicated tracing bus at the final stage of the pipe-line processing. If the data is hit in the cache memory, the trace data can be provided to the tracing circuit without losing real time processing.

Abstract: An integrated circuit device can be inspected in various ways while it is being installed on a circuit board. A bus control unit connects an external memory to a central processing unit in a normal mode. In an inspection mode, the bus control unit connects an inspection control circuit, which has a plurality of registers for temporarily storing instruction codes and data to be processed from an external circuit inspection device, to the central processing unit at a suitable time. When the instruction codes and data from the external circuit inspection are stored in the registers of the inspection control circuit, the central processing unit can be inspected while it is effecting a desired data processing operation.

Abstract: An integrated circuit device can be inspected in various ways while it is being installed on a circuit board. A bus control unit connects an external memory to a central processing unit in a normal mode. In an inspection mode, the bus control unit connects an inspection control circuit, which has a plurality of registers for temporarily storing instruction codes and data to be processed from an external circuit inspection device, to the central processing unit at a suitable time. When the instruction codes and data from the external circuit inspection are stored in the registers of the inspection control circuit, the central processing unit can be inspected while it is effecting a desired data processing operation.

Abstract: A microprocessor includes an interrupt request receiving circuit, a reception control section for controlling the interrupt request receiving circuit to receive an interrupt request in response to a reception control signal, and a control section for setting a supervisor interrupt mode when a supervisor interrupt request is received by the interrupt request receiving circuit in a state in which any supervisor interrupt request is not yet received. At that time, the reception control signal is issued to the reception control section such that the reception control section inhibits the interrupt request receiving circuit from receiving any supervisor interrupt request in the supervisor interrupt mode, and such that the reception control section permits the interrupt request receiving section to receive any user interrupt request in the supervisor interrupt mode. A user interrupt mode is set when a user interrupt request is received by the interrupt request receiving circuit in the supervisor interrupt mode.

Abstract: Characteristic parameters of a torque of a stepping motor and its associated driving current or voltage are measured in advance to providetorque vs. characteristic information data representative of the torque vs. driving current/voltage characterisitcs. Then, the above characteristic parameters are measured again when a real load is applied to a stepping motor as installed with associated mechanical coupling components. An actual load torque is determined by referencing the subsequently measured characteristic parameters to the previously obtained torque vs. characteristic information data. A load inertia moment can be determined by subtracting the motor's rotor inertia moment from a determined inertia moment of the entire system. Efficiency of the motor can be determined by multiplying the output of the measured load torque by the nuber of revolutions per second thereof and dividing this by the power supplied to the motor or driving circuit.