Abstract: Disclosed is a method of removing resist preventing increase of dielectric constant of low permittivity insulating films and preventing remains of resist. Using a resist mask, a protection insulating film, a MSQ film, and a silicon oxide film composing an ILD are RIE dry etched sequentially, and a via is formed on the surface of a substrate for processing reaching the diffusion layer on the substrate for processing. Subsequent process consists of; removing a modified layer formed on the substrate for processing surface because of prior etching using plasma gas by plasma excitation of NH3 gas, and another etching for complete removal of the resist mask by irradiation of hydrogen active species created by hydrogen gas and inert gas, of which example is helium gas or argon gas.

Abstract: To effectively reduce the dielectric constant of an interlayer insulation film including a low dielectric constant film of a porous structure, and easily realize a practical application of a semiconductor device having an ultrafine and highly reliable Damascene wiring structure. A first interlayer insulation film including a porous first low dielectric constant film is formed on a lower layer wiring, and a first side wall metal is formed on a side wall of a via hole arranged in the first low dielectric constant film, and thereafter a first etching stopper layer is etched and the lower layer wiring is exposed. Then, a via plug is embedded into the via hole. In the same manner, after a second side wall metal is arranged on a side wall of a trench in a second interlayer insulation film including a porous second low dielectric constant film, a second etching stopper layer is etched, and an upper layer wiring that connects to the via plug is formed.

Abstract: Disclosed is a method of removing resist preventing increase of dielectric constant of low permittivity insulating films and preventing remains of resist. Using a resist mask, a protection insulating film, a MSQ film, and a silicon oxide film composing an ILD are RIE dry etched sequentially, and a via is formed on the surface of a substrate for processing reaching the diffusion layer on the substrate for processing. Subsequent process consists of; removing a modified layer formed on the substrate for processing surface because of prior etching using plasma gas by plasma excitation of NH3 gas, and another etching for complete removal of the resist mask by irradiation of hydrogen active species created by hydrogen gas and inert gas, of which example is helium gas or argon gas.

Abstract: In resist removal using hydrogen gas, the specific dielectric constant of an insulating film of a low dielectric constant can be reduced and the resist removal speed can be increased. A wafer is loaded on a rotary table in a chamber, and hydrogen mixed gas is introduced into a discharge tube from a gas introduction port, and a ? wave is supplied into the discharge tube via a waveguide, and the mixed gas is excited by plasma, and a hydrogen active species is generated. And, a neutral radical (hydrogen radical) of hydrogen atoms or hydrogen molecules is introduced into the chamber from a gas transport pipe and a resist mask on the surface of the wafer is removed. Here, by a substrate heating system for heating the rotary table and controlling the temperature, the temperature of the wafer is set within the range from 200° C. to 400° C. The processed gas after resist removal is ejected from the chamber through a gas ejection port by an exhaust system.

Abstract: A method for manufacturing a semiconductor device comprises: exposing a surface of a substrate to plasma; and forming an insulating film containing a low dielectric constant material on the surface of the substrate. A method for manufacturing a semiconductor device comprises: forming a modified layer by exposing a surface of a substrate to plasma; and forming an insulating film containing a low dielectric constant material on the modified layer. A method for manufacturing a semiconductor device comprises: forming an adhesion enhancement layer on a substrate; exposing a surface of the adhesion enhancement layer to plasma; and forming a first insulating film on the adhesion enhancement layer.

Abstract: An interlayer insulating film and a first via connected to a diffusion layer in a MOS transistor are formed on the diffusion layer. Then, a low dielectric constant film for a first layer copper interconnection, and the first layer copper interconnection connected to the first via are formed. Then, an etching stopper film, an interlayer insulating film, and a low dielectric constant film for a second layer copper interconnection are formed in this order. Then, a via hole is formed in the etching stopper film and the interlayer insulating film, and a groove is formed in the low dielectric constant film for the second layer copper interconnection. A barrier metal layer is then formed. Thereafter, Ar ions are implanted. At the time, the implantation energy is 50 keV, and the dose is 1×1017 cm−2. A second via and the second layer copper interconnection are formed, and annealing is performed at a temperature of 400° C.

Abstract: A lower electrode film is made to have a crystal grain laminated structure composed of a granular structure crystal grain layer and a columnar structure crystal grain layer. Also, a barrier layer is formed to be a granular structure crystal grain layer made of tantalum nitride containing 10 atm % or more and 50 atm % or less of nitrogen. Thereby, a semiconductor device comprising electrode films wherein both favorable oxygen barrier performance and current conductivity are compatible can be provided.

Abstract: An interlayer insulating film and a first via connected to a diffusion layer in a MOS transistor are formed on the diffusion layer. Then, a low dielectric constant film for a first layer copper interconnection, and the first layer copper interconnection connected to the first via are formed. Then, an etching stopper film, an interlayer insulating film, and a low dielectric constant film for a second layer copper interconnection are formed in this order. Then, a via hole is formed in the etching stopper film and the interlayer insulating film, and a groove is formed in the low dielectric constant film for the second layer copper interconnection. A barrier metal layer is then formed. Thereafter, Ar ions are implanted. At the time, the implantation energy is 50 keV, and the dose is 1×1017 cm−2. A second via and the second layer copper interconnection are formed, and annealing is performed at a temperature of 400° C.

Abstract: A thin-film capacitor having a perovskite-structured polycrystalline oxide thin-film as its dielectric, that exhibits an excellent insulation property is provided. This capacitor comprises a perovskite-structured, polycrystalline oxide thin-film, and top and bottom electrodes located at each side of the thin-film. The perovskite-structured, polycrystalline oxide thin-film has a general formula of ABO3, where A is at least one element selected from the group consisting of bivalent metallic elements, lead, and lanthanum, and B is at least one element selected from the group consisting of quadrivalent metallic elements. A ratio of (A/B) is in a range from 1.1 to 2.0. The oxide thin-film has granular crystal grains. The perovskite-structured, polycrystalline oxide thin-film is formed by forming a perovskite-structured, amorphous oxide thin-film and by crystallizing the perovskite-structured, amorphous oxide thin-film due to heat treatment.

Abstract: The present invention relates to a thin film capacitor that may be used as a stacked capacitor in a memory cell. In a thin film capacitor including a high dielectric constant layer sandwiched by two electrode layers, the high dielectric constant layer includes at least one perovskite-type oxide layer having a columnar structure and at least one perovskite-type oxide layer having a granular structure.

Abstract: A thin-film capacitor having a perovskite-structured polycrystalline oxide thin-film as its dielectric, that exhibits an excellent insulation property is provided. This capacitor comprises a perovskite-structured, polycrystalline oxide thin-film, and top and bottom electrodes located at each side of the thin-film The perovskite-structured, polycrystalline oxide thin-film has a general formula of ABO.sub.3, where A is at least one element selected from the group consisting of bivalent metallic elements, lead, and lanthanum, and B is at least one element selected from the group consisting of quadrivalent metallic elements. A ratio of (A/B) is in a range from 1.1 to 2.0. The oxide thin-film has granular crystal grains. The perovskite-structured, polycrystalline oxide thin-film is formed by forming a perovskite-structured, amorphous oxide thin-film and by crystallizing the perovskite-structured, amorphous oxide thin-film due to heat treatment.