Abstract: A control device has an arithmetic unit that controls onboard devices of a mobile body. The arithmetic unit includes: a first functional section that is actuated regardless of a status of the mobile body and generates a control signal to one or more of the onboard devices; second functional sections that are each actuated in accordance with the status of the mobile body and each generate a control signal to the onboard devices other than the one or more onboard devices; power transmitters disposed in a power transmission path between a power source and the respective second functional sections; and a power source controller that controls supply and cutoff of power to the second functional sections in accordance with the status of the mobile body. The first functional section and the power source controller are mounted on a single chip configured as an integrated circuit.

Abstract: The present disclosure includes a plurality of sensors that acquire information including an external environment of a vehicle, and an arithmetic unit that controls an onboard device of the vehicle in response to the information input from the plurality of sensors. The arithmetic unit includes: a vehicle status identifier that identifies a status of the vehicle; a plurality of functional sections that are actuated in accordance with the status of the vehicle and generate a control signal to be transmitted to the onboard device; and a power source controller that controls supply and cutoff of power to the functional sections so that the power is supplied to a predetermined combination of the functional sections in accordance with the status of the vehicle.

Abstract: When a plurality of output buffer circuits are provided, chip layout size, power consumption, and number of pins of an LSI circuit are reduced. A voltage generation circuit generates reference voltages corresponding respectively to the output buffer circuits. A comparison circuit compares the reference voltages with an output voltage of a dummy buffer circuit. A counter counts a clock signal until a comparison result of the comparison circuit matches. The dummy buffer circuit adjusts output impedance corresponding respectively to the output buffer circuits based on a count value of the counter. Adjustment value holders hold respective count values when a comparison result of the comparison circuit, obtained based on respective corresponding reference voltages, matches. The output buffer circuits respectively adjust output impedances based on respectively held count values.

Abstract: When a plurality of output buffer circuits are provided, chip layout size, power consumption, and number of pins of an LSI circuit are reduced. A voltage generation circuit generates reference voltages corresponding respectively to the output buffer circuits. A comparison circuit compares the reference voltages with an output voltage of a dummy buffer circuit. A counter counts a clock signal until a comparison result of the comparison circuit matches. The dummy buffer circuit adjusts output impedance corresponding respectively to the output buffer circuits based on a count value of the counter. Adjustment value holders hold respective count values when a comparison result of the comparison circuit, obtained based on respective corresponding reference voltages, matches. The output buffer circuits respectively adjust output impedances based on respectively held count values.

Abstract: Disclosed is an output buffer circuit including a first differential transistor pair for differentially receiving a data signal from a differential input pair; and a second differential transistor pair for differentially receiving an emphasis data signal from another differential input pair; a pair of output resistor circuits via which the drains of first and second differential transistor pairs are connected to a power supply, said output resistor circuits each including a transistor; and a logic circuit adapted for receiving the data signal and the emphasis signal and for supplying a control signal which is of first and second values at the time of preemphasis and at other times to the transistors of the output resistor circuit, wherein the output resistance is relatively made larger at the time of emphasis, while being relatively smaller at the time of deemphasis.

Abstract: Disclosed is an output buffer circuit including a first differential transistor pair for differentially receiving a data signal from a differential input pair; and a second differential transistor pair for differentially receiving an emphasis data signal from another differential input pair; a pair of output resistor circuits via which the drains of first and second differential transistor pairs are connected to a power supply, said output resistor circuits each including a transistor; and a logic circuit adapted for receiving the data signal and the emphasis signal and for supplying a control signal which is of first and second values at the time of preemphasis and at other times to the transistors of the output resistor circuit, wherein the output resistance is relatively made larger at the time of emphasis, while being relatively smaller at the time of deemphasis.