Patents by Inventor Shuji Tobashi

Shuji Tobashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10573531
    Abstract: A method of manufacturing a semiconductor device includes forming a first photoresist film over a substrate, exposing a first pattern including an alignment pattern in a first region, forming, on the substrate, an alignment mark corresponding to the exposed alignment pattern, forming a second photoresist film over the substrate on which the alignment mark is formed, dividing a second pattern into a plurality of regions and exposing the divided regions separately in a second region while performing positioning with respect to the alignment mark, and developing the second photoresist film and forming the second photoresist film having the second pattern, wherein at least a part of the second region is located outside an effective exposure region of an exposure apparatus in exposure of the first pattern.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: February 25, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Shuji Tobashi, Masayuki Tsuchiya
  • Publication number: 20190057939
    Abstract: A method of manufacturing a semiconductor device includes forming a first photoresist film over a substrate, exposing a first pattern including an alignment pattern in a first region, forming, on the substrate, an alignment mark corresponding to the exposed alignment pattern, forming a second photoresist film over the substrate on which the alignment mark is formed, dividing a second pattern into a plurality of regions and exposing the divided regions separately in a second region while performing positioning with respect to the alignment mark, and developing the second photoresist film and forming the second photoresist film having the second pattern, wherein at least a part of the second region is located outside an effective exposure region of an exposure apparatus in exposure of the first pattern.
    Type: Application
    Filed: August 9, 2018
    Publication date: February 21, 2019
    Inventors: Shuji Tobashi, Masayuki Tsuchiya
  • Patent number: 9966395
    Abstract: A solid-state image sensor is provided. The sensor includes a first transistor including a first diffusion region, a second transistor including a second diffusion region and an insulation film arranged over these transistors. The insulation film includes a first and a second film. A first portion of the first diffusion region covered with the insulation film includes a second portion covered with only the second film. A third portion of the second diffusion region covered with the insulation film includes a fourth portion covered with the first and second film. A stress in the fourth portion is larger than the second portion. A proportion of an area of the first portion except the second portion to an area of the first portion is lower than a proportion of an area of the fourth portion to an area of the third portion.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: May 8, 2018
    Assignee: Canon Kabushiki Kaisha
    Inventors: Satoshi Kato, Shuji Tobashi, Masayuki Tsuchiya
  • Publication number: 20170229498
    Abstract: A solid-state image sensor is provided. The sensor includes a first transistor including a first diffusion region, a second transistor including a second diffusion region and an insulation film arranged over these transistors. The insulation film includes a first and a second film. A first portion of the first diffusion region covered with the insulation film includes a second portion covered with only the second film. A third portion of the second diffusion region covered with the insulation film includes a fourth portion covered with the first and second film. A stress in the fourth portion is larger than the second portion. A proportion of an area of the first portion except the second portion to an area of the first portion is lower than a proportion of an area of the fourth portion to an area of the third portion.
    Type: Application
    Filed: January 25, 2017
    Publication date: August 10, 2017
    Inventors: Satoshi Kato, Shuji Tobashi, Masayuki Tsuchiya
  • Publication number: 20050239267
    Abstract: A substrate manufacturing method includes steps of preparing a bonded substrate stack formed by bonding a second substrate to a first substrate having an insulator at least on a surface, forming a gettering layer to capture a metal contamination on the surface of the bonded substrate stack to form a composite substrate stack, annealing the composite substrate stack, and removing the gettering layer from the composite substrate stack.
    Type: Application
    Filed: April 21, 2005
    Publication date: October 27, 2005
    Applicant: Canon Kabushiki Kaisha
    Inventor: Shuji Tobashi
  • Patent number: 6537924
    Abstract: A method of chemically growing a thin film in a gas phase using a rotary gaseous phase thin film growth apparatus which feeds a material gas by flowing down the gas from above to a surface of a rotating silicon semiconductor substrate to grow a thin film on a surface of said silicon semiconductor substrate in a method of chemically growing a thin film that a thin film-growing reaction is done wherein: monosilane gas is used as an effective component of the material gas to grow the thin film under a reduced pressure of from 2.7×102 to 6.7×103 Pa with the number of rotations of said silicon semiconductor substrate being from 500 to 2000 min−1 and at a reaction temperature of from 600° C. to 800° C.
    Type: Grant
    Filed: August 6, 2001
    Date of Patent: March 25, 2003
    Assignees: Toshiba Ceramics, Co., Ltd., Toshiba Kikai Kabushikikaisha
    Inventors: Shuji Tobashi, Tadashi Ohashi, Shinichi Mitani, Hideki Arai, Hidenori Takahashi
  • Publication number: 20020045009
    Abstract: A method of chemically growing a thin film in a gas phase using a rotary gaseous phase thin film growth apparatus which feeds a material gas by flowing down the gas from above to a surface of a rotating silicon semiconductor substrate to grow a thin film on a surface of said silicon semiconductor substrate in a method of chemically growing a thin film that a thin film-growing reaction is done wherein: monosilane gas is used as an effective component of the material gas to grow the thin film under a reduced pressure of from 2.7×102 to 6.7×103 Pa with the number of rotations of said silicon semiconductor substrate being from 500 to 2000 min−1 and at a reaction temperature of from 600° C. to 800° C.
    Type: Application
    Filed: August 6, 2001
    Publication date: April 18, 2002
    Applicant: TOSHIBA CERAMICS CO., LTD.
    Inventors: Shuji Tobashi, Tadashi Ohashi, Shinichi Mitani, Hideki Arai, Hidenori Takahashi
  • Publication number: 20010052316
    Abstract: An apparatus for reduced-pressure gaseous phase epitaxial growth by suppressing contamination upon the machine parts constituting the rotary mechanical portion and suppressing contamination upon the semiconductor wafer by maintaining the pressure in the rotary mechanical portion to lie within a particular range, and a method of controlling the above apparatus.
    Type: Application
    Filed: May 16, 2001
    Publication date: December 20, 2001
    Applicant: TOSHIBA CERAMICS CO., LTD
    Inventors: Katsuyuki Iwata, Tadashi Ohashi, Shuji Tobashi, Shinichi Mitani, Hideki Arai, Hideki Ito
  • Patent number: 6250914
    Abstract: The present invention provides a wafer heating device which can improve uniformity of a temperature distribution within a surface area of a wafer, with a relatively simple structure. A wafer is supported on a susceptor of annular shape. A first heater of disc shape is disposed below the wafer, and a second heater of annular shape is disposed to surround the first heater. Radiation thermometers are arranged at a ceiling portion of a reaction chamber. The first radiation thermometer measures a temperature of a central area of the wafer, the second radiation thermometer measures a temperature of a peripheral area of the wafer, and the third radiation thermometer measures a temperature of the susceptor. The first heater and the second heater are controlled by independent closed loops. When a wafer is set on the susceptor, a power of the second heater is controlled by using a value measured by the second radiation thermometer as a feedback signal.
    Type: Grant
    Filed: April 21, 2000
    Date of Patent: June 26, 2001
    Assignees: Toshiba Machine Co., Ltd, Toshiba Ceramics Co., Ltd.
    Inventors: Hirofumi Katsumata, Hideki Ito, Hidenori Takahashi, Tadashi Ohashi, Shuji Tobashi, Katsuyuki Iwata
  • Patent number: 6245313
    Abstract: The object of the present invention is to provide a process for manufacturing a product of glassy carbon, having endurance strength to fatigue at elevated temperature, and to thermal fatigue. After curing the material resin in a mold, the cured resin is baked to obtain a glassy carbon piece. The piece is then machined into a predetermined shape. Subsequently, the surface of the piece resulted after machining, is impregnated with the resin. Further, the resin-impregnated piece is baked so as to transform the impregnated resin into glassy carbon.
    Type: Grant
    Filed: May 17, 1999
    Date of Patent: June 12, 2001
    Assignees: Toshiba Machine Co., Ltd., Toshiba Ceramics Co., Ltd.
    Inventors: Kunihiko Suzuki, Takaaki Honda, Shinichi Mitani, Tadashi Ohashi, Shuji Tobashi
  • Patent number: 5744401
    Abstract: A silicon wafer is mirror-polished until obtaining surface roughness Ra of 0.70-1.00 nm, Rq of 0.80-1.10 nm, or Rt of 4.50-7.00 nm. The resulting wafer is heat-treated at a temperature not lower than 1,200.degree. C. for 30 minutes to 4 hours in a hydrogen gas atmosphere. According to another aspect, a silicon wafer is mirror-polished until obtaining surface roughness values Ra' of 0.08-0.70 nm, rms of 0.10-0.90 nm, and P-V of 0.80-5.80 nm in a square area of 90 .mu.m by 90 .mu.m, and surface roughness values Ra' of 0.13-0.40 nm, rms of 0.18-0.50 nm, and P-V of 1.30-2.50 nm in a square area of 500 nm by 500 nm. The resulting wafer is heat-treated at 1,100.degree.-1,300.degree. C. for 30 minutes to 4 hours in a hydrogen gas atmosphere.
    Type: Grant
    Filed: March 22, 1996
    Date of Patent: April 28, 1998
    Assignee: Toshiba Ceramics Co., Ltd.
    Inventors: Hiroshi Shirai, Jun Yoshikawa, Youji Ogawa, Kazuhiko Kashima, Kazuya Ookubo, Yukari Kohtari, Norihiro Shimoi, Masayuki Sanada, Shuji Tobashi