Abstract: A physical process ID (PPID) is stored for each cache block of each set, and a MAX WAY number for each PPID value is stored for each of index values #1 to #n. A MAX WAY number corresponding to a certain PPID value in a certain index value indicates the maximum number of cache blocks having the PPID value, which can be stored in the index value. The number of ways at the time of a cache miss is controlled not to exceed the MAX WAY number of each PPID value for each index value.

Abstract: A prefetch processing apparatus includes a central-processing-unit monitor unit that monitors processing states of the central processing unit in association with time elapsed from start time of executing a program. A cache-miss-data address obtaining unit obtains cache-miss-data addresses in association with the time elapsed from the start time of executing the program, and a cycle determining unit determines a cycle of time required for executing the program. An identifying unit identifies a prefetch position in a cycle in which a prefetch-target address is to be prefetched by associating the cycle determined by the cycle determining unit with the cache-miss data addresses obtained by the cache-miss-data address obtaining unit. The prefetch-target address is an address of data on which prefetch processing is to be performed.

Abstract: The execution status of pipeline processing is highly visualized by appropriately displaying processes forming loops in a simplified manner. A loop-information storage unit stores loop-defining information specifying the address of an instruction that causes a pipeline process forming a loop. An operation-information storage unit stores operation information that includes the address of an instruction input into a pipeline and information indicating the execution status of a pipeline process caused by the instruction. A loop determination unit determines whether each pipeline process indicated by the operation information forms a loop by referring to the loop-defining information. An output unit outputs visualization information indicating, in a visually comprehensible manner, the execution status of a pipeline process that has been determined to form a loop for a predetermined number of executions of the loop and the execution status of a pipeline process that has been determined to form no loop.

Abstract: A cache memory for operating in accordance with a multi-way set associative system, the cache memory includes an identification information storage for storing an identification information for identifying a requesting element of a memory access request corresponding to a cache block specified by a received memory access request, a replacement cache block candidate determinator for determining, upon an occurrence of a cache miss corresponding to the memory access request, a candidate of the cache block for replacing, on the basis of the identification information attached to the memory access request and the identification information stored in the identification information storage corresponding to the cache block specified by the memory access request, and a replacement cache block selector for selecting a replacement cache block from the candidate.

Abstract: A communication performance analyzing program, a communication performance analyzing apparatus and a communication performance analyzing method make it possible to highly reliably grasp the communication performance of a computer system by automatically analyzing the communication performance. The communication performance analyzing program that causes a computer to analyze a data tendency of communication performance of a plurality of execution periods of a computer system formed by connecting a plurality of computers by a network, the program comprises a communication time acquisition step S2 that acquires communication time data among the computers of the computer system and a statistical analysis step S3 that analyzes the tendency of communication performance data of each execution period of the computer system, using the communication time among the computers, by statistically analyzing the communication time data acquired by the communication time acquisition step.

Abstract: An information processing system performs a prefetch for predicting data that is likely to be accessed by a central processing unit, reading the predicted data from a main memory, and storing the data in a cache area in advance. The information processing system includes a usage information storage unit that stores therein usage information indicating whether prefetched data has been accessed; and a usage information writing unit that writes the usage information of the prefetched data in the usage information storage unit.

Abstract: A cache memory having a sector function, operating in accordance with a set associative system, and performing a cache operation to replace data in a cache block in the cache way corresponding to a replacement cache way determined upon an occurrence of a cache miss comprises: storing sector ID information in association with each of the cache ways in the cache block specified by a memory access request; determining, upon the occurrence of the cache miss, replacement way candidates, in accordance with sector ID information attached to the memory access request and the stored sector ID information; selecting and outputting a replacement way from the replacement way candidates; and updating the stored sector ID information in association with each of the cache ways in the cache block specified by the memory access request, to the sector ID information attached to the memory access request.

Abstract: The system provides a technique for detecting changes in behavior of a computer system. An address data storing unit obtains an address being accessed by a CPU at prescribed sampling intervals, stores address data comprising the address and its acquisition time in an address record table in time series. Then an executed process detector detects the name of the process that was executed when the address data was obtained, and sets the process name for the address data in the address record table. When an analysis request specifying an analysis time period is made, an analyzer counts up each of the process names included in the address data being stored in the address record table for each specified analysis time period, and analyzes the breakdown of executed processes for each analysis time period. Then a display unit displays the analysis result of the analyzer.

Abstract: The execution status of pipeline processing is highly visualized by appropriately displaying processes forming loops in a simplified manner. A loop-information storage unit stores loop-defining information specifying the address of an instruction that causes a pipeline process forming a loop. An operation-information storage unit stores operation information that includes the address of an instruction input into a pipeline and information indicating the execution status of a pipeline process caused by the instruction. A loop determination unit determines whether each pipeline process indicated by the operation information forms a loop by referring to the loop-defining information. An output unit outputs visualization information indicating, in a visually comprehensible manner, the execution status of a pipeline process that has been determined to form a loop for a predetermined number of executions of the loop and the execution status of a pipeline process that has been determined to form no loop.

Abstract: A prefetch processing apparatus includes a central-processing-unit monitor unit that monitors processing states of the central processing unit in association with time elapsed from start time of executing a program. A cache-miss-data address obtaining unit obtains cache-miss-data addresses in association with the time elapsed from the start time of executing the program, and a cycle determining unit determines a cycle of time required for executing the program. An identifying unit identifies a prefetch position in a cycle in which a prefetch-target address is to be prefetched by associating the cycle determined by the cycle determining unit with the cache-miss data addresses obtained by the cache-miss-data address obtaining unit. The prefetch-target address is an address of data on which prefetch processing is to be performed.

Abstract: A communication performance analyzing program, a communication performance analyzing apparatus and a communication performance analyzing method make it possible to highly reliably grasp the communication performance of a computer system by automatically analyzing the communication performance. The communication performance analyzing program that causes a computer to analyze a data tendency of communication performance of a plurality of execution periods of a computer system formed by connecting a plurality of computers by a network, the program comprises a communication time acquisition step S2 that acquires communication time data among the computers of the computer system and a statistical analysis step S3 that analyzes the tendency of communication performance data of each execution period of the computer system, using the communication time among the computers, by statistically analyzing the communication time data acquired by the communication time acquisition step.

Abstract: A computer-readable recording medium storing a system analysis program capable of detecting changes in behavior occurring in a very short time without fail. An address data storing unit obtains an address being accessed by a CPU at prescribed sampling intervals, stores address data comprising the address and its acquisition time in an address record table in time series. Then an executed process detector detects the name of the process that was executed when the address data was obtained, and sets the process name for the address data in the address record table. When an analysis request specifying an analysis time period is made, an analyzer counts up each of the process names included in the address data being stored in the address record table for each specified analysis time period, and analyzes the breakdown of executed processes for each analysis time period. Then a display unit displays the analysis result of the analyzer.

Abstract: A recording medium which is readable by a computer stores a performance analyzing program for searching for a node that is peculiar in performance in a cluster system, as well as unknown problems. The performance analyzing program enables the computer to function as various functional units. A performance data analyzing unit collects performance data of nodes which make up the cluster system from performance data storage unit for storing a plurality of types of performance data of the nodes, and analyzes performance values of the nodes based on the collected performance data. A classifying unit classifies the nodes into a plurality of groups by statistically processing the performance data collected by the performance data analyzing unit according to a predetermined classifying condition.

Abstract: In an accounting apparatus, a conflict determination unit determines whether or not the accounting mode is in a conflict state where a process is executing in another logical CPU and stores the determination result in an accounting information storage unit, when a process of the user starts to be executed in a logical CPU of an SMT processor. And a CPU use time acquisition unit collects the CPU use time of the process in the conflict state or the non-conflict state distinctively and stores it in an accounting information storage unit. Thereafter, a CPU use time conversion unit converts the CPU use time in the conflict state, with a predetermined weighting, based on the CPU use time in the conflict state and the non-conflict state, after the end of executing the process, and an accounting calculation unit calculates the accounting amount for the process from an effective use time.

Abstract: In a circular fluorescent lamp unit comprising: a glass bulb 1 which is bent into a ring shape with both ends abutting on each other, has phosphor powder coated on an inner wall thereof, has electrodes provided at the respective ends in an inner space thereof and has mercury and inert gas sealed therein; and a cap which has connection pins used for electrically connecting the electrodes in the glass bulb with the outside and is attached so as to cut across the both ends of the glass bulb, a tube outer diameter of the glass bulb 1 is 13 mm to 20 mm, a ring outer diameter of the ring is 145 mm to 170 mm, lamp wattage is not more than 20 W, and lighting is carried out with a high frequency which is not less than 10 kHz.

Abstract: In a circular fluorescent lamp unit comprising: a glass bulb 1 which is bent into a ring shape with both ends abutting on each other, has phosphor powder coated on an inner wall thereof, has electrodes provided at the respective ends in an inner space thereof and has mercury and inert gas sealed therein; and a cap which has connection pins used for electrically connecting the electrodes in the glass bulb with the outside and is attached so as to cut across the both ends of the glass bulb, a tube outer diameter of the glass bulb 1 is 13 mm to 20 mm, a ring outer diameter of the ring is 145 mm to 170 mm, lamp wattage is not more than 20 W, and lighting is carried out with a high frequency which is not less than 10 kHz.