Abstract: A method for manufacturing a trench isolation structure comprising forming a shallow trench having a wider upper section and a narrower lower section in a wafer surface, removing part of the silicon oxide by etching, forming a silicon oxide corner structure at a corner at a top corner of the shallow trench by thermal oxidation, depositing silicon nitride on the wafer surface to cover surfaces of the shallow trench silicon oxide and the silicon oxide corner structure, dry etching the silicon nitride on the shallow trench silicon oxide surface thereby forming masking silicon nitride residues extending into the trench, etching downwards to form a deep trench, forming silicon oxide layers on a side wall and the bottom of the deep trench, depositing polycrystalline silicon in the shallow and deep trenches, removing the silicon nitride, and forming silicon oxide in the shallow trench to cover the polycrystalline silicon.

Abstract: Disclosed is a method for manufacturing an isolation structure for LDMOS, the method comprising: forming a first groove on the surface of a wafer; filling the first groove with silicon oxide; removing part of the surface of the silicon oxide within the first groove by means of etching; forming a silicon oxide corner structure at the corner of the top of the first groove by means of thermal oxidation; depositing a nitrogen-containing compound on the surface of the wafer to cover the surface of the silicon oxide within the first groove and the surface of the silicon oxide corner structure; dry-etching the nitrogen-containing compound to remove the nitrogen-containing compound from the surface of the silicon oxide within the first groove, and thereby forming a nitrogen-containing compound side wall residue; with the nitrogen-containing compound side wall residue as a mask, continuing to etch downwards to form a second groove; forming a silicon oxide layer on the side wall and the bottom of the second groove; rem

Abstract: A gate structure of a semiconductor device, includes: a trench gate and a planar gate including a plurality of polysilicon structures (406) separated from each other; the gate structure of the semiconductor device further includes a well region (503) being adjacent to the trench gate and being disposed under the planar gate; a first conduction type doped region (504) being disposed in the well region (503) and including a plurality of regions separated from each other, wherein each region is disposed under adjacent polysilicon structures (406), and respective regions are electrically connected to the planar gate; and a source (504a) being disposed in the well region (503); wherein the trench gate includes: a silicon oxide filler (202) including a side wall silicon oxide and a bottom silicon oxide; a control gate (402) being located over the trench gate, wherein a side wall of the control gate is enclosed by the side wall silicon oxide, and the control gate (402) is electrically-connected to the planar gate; a

Abstract: A lateral insulated-gate bipolar transistor and a manufacturing method therefor. The lateral insulated-gate bipolar transistor comprises a substrate, an anode terminal and a cathode terminal on the substrate, and a drift region and a gate electrode located between the anode terminal and the cathode terminal. The anode terminal comprises an N-shaped buffer zone on the substrate, a P well in the N-shaped buffer zone, an N+ zone in the P well, a groove located above the N+ zone and partially encircled by the P well, polycrystalline silicon in the groove, P+ junctions at two sides of the groove, and N+ junctions at two sides of the P+ junctions.

Abstract: A gate structure of a semiconductor device, includes: a trench gate and a planar gate including a plurality of polysilicon structures (406) separated from each other; the gate structure of the semiconductor device further includes a well region (503) being adjacent to the trench gate and being disposed under the planar gate; a first conduction type doped region (504) being disposed in the well region (503) and including a plurality of regions separated from each other, wherein each region is disposed under adjacent polysilicon structures (406), and respective regions are electrically connected to the planar gate; and a source (504a) being disposed in the well region (503); wherein the trench gate includes: a silicon oxide filler (202) including a side wall silicon oxide and a bottom silicon oxide; a control gate (402) being located over the trench gate, wherein a side wall of the control gate is enclosed by the side wall silicon oxide, and the control gate (402) is electrically-connected to the planar gate; a

Abstract: Disclosed is a method for manufacturing an isolation structure for LDMOS, the method comprising: forming a first groove on the surface of a wafer; filling the first groove with silicon oxide; removing part of the surface of the silicon oxide within the first groove by means of etching; forming a silicon oxide corner structure at the corner of the top of the first groove by means of thermal oxidation; depositing a nitrogen-containing compound on the surface of the wafer to cover the surface of the silicon oxide within the first groove and the surface of the silicon oxide corner structure; dry-etching the nitrogen-containing compound to remove the nitrogen-containing compound from the surface of the silicon oxide within the first groove, and thereby forming a nitrogen-containing compound side wall residue; with the nitrogen-containing compound side wall residue as a mask, continuing to etch downwards to form a second groove; forming a silicon oxide layer on the side wall and the bottom of the second groove; rem

Abstract: A lateral diffused metal oxide semiconductor field effect transistor, comprising a substrate, a gate, a source, a drain, a body region, a field oxide region between the source and drain, and a first well region and second well region on the substrate. The second well region below the gate is provided with a plurality of gate doped regions, and a polycrystalline silicon gate of the gate is a multi-segment structure, each segment being separated from the others, with each gate doped region being disposed below the spaces between each segment of the polycrystalline silicon gate. Each of the gate doped regions is electrically connected to the segment that is in a direction nearest the source from among the two polycrystalline silicon gate segments on either side thereof.

Abstract: A lateral insulated-gate bipolar transistor and a manufacturing method therefor. The lateral insulated-gate bipolar transistor comprises a substrate, an anode terminal and a cathode terminal on the substrate, and a drift region and a gate electrode located between the anode terminal and the cathode terminal. The anode terminal comprises an N-shaped buffer zone on the substrate, a P well in the N-shaped buffer zone, an N+ zone in the P well, a groove located above the N+ zone and partially encircled by the P well, polycrystalline silicon in the groove, P+ junctions at two sides of the groove, and N+ junctions at two sides of the P+ junctions.

Abstract: A laterally diffused metal oxide semiconductor field-effect transistor, comprising a substrate (110), a source electrode (150), a drain electrode (140), a body region (160), and a well region on the substrate, the well region comprising: an insertion-type well (122) having P-type doping, being arranged below the drain electrode and being connected to the drain electrode; N wells (124), arranged on two sides of the insertion-type well; and P wells (126), arranged next to the N wells and being connected to the N wells; the source electrode and the body region are arranged in the P well.

Abstract: A laterally diffused metal-oxide semiconductor field-effect transistor, comprising a substrate, a first conductivity type well region, a second conductivity type well region, a drain electrode in the first conductivity type well region, a source electrode and a body region in the second conductivity type well region, and a gate electrode arranged across surfaces of the first conductivity type well region and the second conductivity type well region, and also comprising a floating layer ring arranged on the top of the first conductivity type well region and located between the gate electrode and the drain electrode and a plurality of groove polysilicon electrodes running through the floating layer ring and stretching into the first conductivity type well region.

Abstract: A lateral diffused metal oxide semiconductor field effect transistor, comprising a substrate, a gate, a source, a drain, a body region, a field oxide region between the source and drain, and a first well region and second well region on the substrate. The second well region below the gate is provided with a plurality of gate doped regions, and a polycrystalline silicon gate of the gate is a multi-segment structure, each segment being separated from the others, with each gate doped region being disposed below the spaces between each segment of the polycrystalline silicon gate. Each of the gate doped regions is electrically connected to the segment that is in a direction nearest the source from among the two polycrystalline silicon gate segments on either side thereof.

Abstract: A laterally diffused metal-oxide semiconductor field-effect transistor, comprising a substrate, a first conductivity type well region, a second conductivity type well region, a drain electrode in the first conductivity type well region, a source electrode and a body region in the second conductivity type well region, and a gate electrode arranged across surfaces of the first conductivity type well region and the second conductivity type well region, and also comprising a floating layer ring arranged on the top of the first conductivity type well region and located between the gate electrode and the drain electrode and a plurality of groove polysilicon electrodes running through the floating layer ring and stretching into the first conductivity type well region.

Abstract: Provided is a lateral insulated-gate bipolar transistor (LIGBT), comprising a substrate (10), an anode terminal and a cathode terminal on the substrate (10), and a drift region (30) and a gate (61) located between the anode terminal and the cathode terminal. The anode terminal comprises a P-type buried layer (52) on the substrate (10), an N-type buffer region (54) on the P-type buried layer (52), and a P+ collector region (56) on the surface of the N-type buffer region (54). The LIGBT further comprises a trench gate adjacent to the anode terminal, wherein the trench gate penetrates from the surfaces of the N-type buffer region (54) and the P+ collector region (56) to the P-type buried layer (52), and the trench gate comprises an oxidation layer (51) on the inner surface of a trench and polysilicon (53) filled into the oxidation layer.

Abstract: Provided is a laterally diffused metal-oxide-semiconductor field-effect transistor, comprising a substrate (110), a source (150), a drain (140), a body region (160), a P-type field-limiting ring (135), and a well region on the substrate (110); the well region comprises an inserted well (122), which has P-type doping and is disposed below the drain and connected to the drain; N wells (124) disposed at the two sides of the inserted well (122); a P well (126) disposed next to the N well (124) and connected to the N well (124); a P-type field-limiting ring (135), which is disposed inside the N well (124), is a closed ring-shaped structure, and is located at the periphery below the drain (140); the inserted well (122) extends in its longitudinal direction to the position where it is in contact with said P-type field-limiting ring (135); the source (150) and the body region (160) are disposed inside the P well (126).

Abstract: Provided is a laterally diffused metal-oxide-semiconductor field-effect transistor, comprising a substrate (110), a source (150), a drain (140), a body region (160), a P-type field-limiting ring (135), and a well region on the substrate (110); the well region comprises an inserted well (122), which has P-type doping and is disposed below the drain and connected to the drain; N wells (124) disposed at the two sides of the inserted well (122); a P well (126) disposed next to the N well (124) and connected to the N well (124); a P-type field-limiting ring (135), which is disposed inside the N well (124), is a closed ring-shaped structure, and is located at the periphery below the drain (140); the inserted well (122) extends in its longitudinal direction to the position where it is in contact with said P-type field-limiting ring (135); the source (150) and the body region (160) are disposed inside the P well (126).

Abstract: A laterally diffused metal oxide semiconductor field-effect transistor, comprising a substrate (110), a source electrode (150), a drain electrode (140), a body region (160), and a well region on the substrate, the well region comprising: an insertion-type well (122) having P-type doping, being arranged below the drain electrode and being connected to the drain electrode; N wells (124), arranged on two sides of the insertion-type well; and P wells (126), arranged next to the N wells and being connected to the N wells; the source electrode and the body region are arranged in the P well.

Abstract: Provided is a lateral insulated-gate bipolar transistor (LIGBT), comprising a substrate (10), an anode terminal and a cathode terminal on the substrate (10), and a drift region (30) and a gate (61) located between the anode terminal and the cathode terminal. The anode terminal comprises a P-type buried layer (52) on the substrate (10), an N-type buffer region (54) on the P-type buried layer (52), and a P+ collector region (56) on the surface of the N-type buffer region (54). The LIGBT further comprises a trench gate adjacent to the anode terminal, wherein the trench gate penetrates from the surfaces of the N-type buffer region (54) and the P+ collector region (56) to the P-type buried layer (52), and the trench gate comprises an oxidation layer (51) on the inner surface of a trench and polysilicon (53) filled into the oxidation layer.

Abstract: A lateral insulated gate bipolar transistor comprises a substrate (10); an anode terminal located on the substrate, comprising: an N-type buffer region (51) located on the substrate (10); a P well (53) located in the N-type buffer region; an N-region (55) located in the P well (53); two P+ shallow junctions (57) located on a surface of the P well (53); and an N+ shallow junction (59) located between the two P+ shallow junctions (57); a cathode terminal located on the substrate; a draft region (30) between the anode terminal and cathode terminal; and a gate (62) between the anode terminal and cathode terminal.

Abstract: A lateral insulated gate bipolar transistor comprises a substrate (10); an anode terminal located on the substrate, comprising: an N-type buffer region (51) located on the substrate (10); a P well (53) located in the N-type buffer region; an N-region (55) located in the P well (53); two P+ shallow junctions (57) located on a surface of the P well (53); and an N+ shallow junction (59) located between the two P+ shallow junctions (57); a cathode terminal located on the substrate; a draft region (30) between the anode terminal and cathode terminal; and a gate (62) between the anode terminal and cathode terminal.