Patents by Inventor Shuli PAN

Shuli PAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10510743
    Abstract: An Electro-Static-Discharge (ESD) protection device has a Fin Field-Effect Transistor (FinFET) with a silicon fin with a step separating a top fin and a bottom fin. The gate wraps around the top fin but not the bottom fin. Normal gate-controlled channel conduction occurs in the top fin between a source and a drain in the top fin. Underneath the conducting channel is a buried conducting region in the bottom fin that conducts after a breakdown voltage is reached during ESD. A ledge, abrupt slope change in the sidewalls of the fin, or a doping increase occurs at the step between the top fin and bottom fin. The bottom fin is 2-3 times wider than the top fin, causing the resistance of the buried conducting region to be 2-3 times less than the resistance of the conducting channel, steering breakdown current away from the channel, reducing failures during breakdown.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: December 17, 2019
    Assignee: Hong Kong Applied Science and Technology Research Institute Company, Limited
    Inventors: Xiaoyong Han, Xiao Huo, Shuli Pan
  • Patent number: 10504886
    Abstract: An Electro-Static-Discharge (ESD) input-protection device has an NPNP structure of a N+ cathode formed in a FINFET fin or highly-doped region over a floating P-well, and a P+ fin or highly-doped region anode formed over a floating N-well that touches the floating P-well. The floating P-well is surrounded by an isolating N-well and has a deep N-well underneath to completely isolate the floating P-well from the p-type substrate. No well taps are formed in the floating wells or in the isolating N-wells. The floating P-well and the floating N-well are thus truly floating at all times. Since the wells are floating, the NPNP structure appears as three junction diodes in series, which has a lower capacitance than a single diode that the NPNP structure would appear as when one of the wells was shorted or biased. During an ESD event the NPNP structure behaves as a single diode.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: December 10, 2019
    Assignee: Hong Kong Applied Science and Technology Research Institute Company, Limited
    Inventors: Chun-Kit Yam, Chenyue Ma, Shuli Pan
  • Publication number: 20190027470
    Abstract: An Electro-Static-Discharge (ESD) protection device has a Fin Field-Effect Transistor (FinFET) with a silicon fin with a step separating a top fin and a bottom fin. The gate wraps around the top fin but not the bottom fin. Normal gate-controlled channel conduction occurs in the top fin between a source and a drain in the top fin. Underneath the conducting channel is a buried conducting region in the bottom fin that conducts after a breakdown voltage is reached during ESD. A ledge, abrupt slope change in the sidewalls of the fin, or a doping increase occurs at the step between the top fin and bottom fin. The bottom fin is 2-3 times wider than the top fin, causing the resistance of the buried conducting region to be 2-3 times less than the resistance of the conducting channel, steering breakdown current away from the channel, reducing failures during breakdown.
    Type: Application
    Filed: July 18, 2017
    Publication date: January 24, 2019
    Inventors: Xiaoyong HAN, Xiao HUO, Shuli PAN