Patents by Inventor Shu-Ming Huang

Shu-Ming Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9035317
    Abstract: A pixel structure disposed on a substrate is provided. The pixel structure includes a gate electrode, a first gate insulation layer, a pixel electrode, a second gate insulation layer, a channel layer, a source electrode, a drain electrode and a common electrode. The gate electrode is disposed on the substrate and covered by the first gate insulation layer. The pixel electrode is disposed on the first gate insulation layer and covered by the second gate insulation layer. The pixel electrode is located between the first and the second gate insulation layers. The second gate insulation layer has a first contact opening exposing a portion of the pixel electrode. The channel layer is disposed on the second gate insulation layer. The drain electrode electrically connected to the pixel electrode. The source electrode is disposed on the second gate insulation layer. The common electrode is disposed on the second gate insulation layer.
    Type: Grant
    Filed: September 2, 2013
    Date of Patent: May 19, 2015
    Assignee: Au Optronics Corporation
    Inventors: Shu-Ming Huang, Yi-Ji Tsai, Chung-Li Chao, Wan-Jung Tseng
  • Publication number: 20140339563
    Abstract: A pixel structure disposed on a substrate is provided. The pixel structure includes a gate electrode, a first gate insulation layer, a pixel electrode, a second gate insulation layer, a channel layer, a source electrode, a drain electrode and a common electrode. The gate electrode is disposed on the substrate and covered by the first gate insulation layer. The pixel electrode is disposed on the first gate insulation layer and covered by the second gate insulation layer. The pixel electrode is located between the first and the second gate insulation layers. The second gate insulation layer has a first contact opening exposing a portion of the pixel electrode. The channel layer is disposed on the second gate insulation layer. The drain electrode electrically connected to the pixel electrode. The source electrode is disposed on the second gate insulation layer. The common electrode is disposed on the second gate insulation layer.
    Type: Application
    Filed: September 2, 2013
    Publication date: November 20, 2014
    Applicant: Au Optronics Corporation
    Inventors: Shu-Ming Huang, Yi-Ji Tsai, Chung-Li Chao, Wan-Jung Tseng
  • Patent number: 8652899
    Abstract: The present invention provides a pixel structure including a substrate, a patterned electrode disposed on the substrate, a first insulating layer disposed on the patterned electrode, a common electrode disposed on the first insulating layer, a second insulating layer disposed on the common electrode, and a drain disposed on the second insulating layer. The first insulating layer has a first through hole, and the second insulating layer has a second through hole. The drain includes a first portion electrically connected to the patterned electrode via the first through hole and the second through hole, and a second portion extending onto the common electrode. The common electrode is coupled with the patterned electrode to form a first storage capacitor and is coupled with the second portion to form a second storage capacitor.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: February 18, 2014
    Assignee: AU Optronics Corp.
    Inventors: Chien-Chih Lee, Pei-Yi Shen, Ching-Yang Cheng, Shu-Ming Huang
  • Publication number: 20130323889
    Abstract: The present invention provides a pixel structure including a substrate, a patterned electrode disposed on the substrate, a first insulating layer disposed on the patterned electrode, a common electrode disposed on the first insulating layer, a second insulating layer disposed on the common electrode, and a drain disposed on the second insulating layer. The first insulating layer has a first through hole, and the second insulating layer has a second through hole. The drain includes a first portion electrically connected to the patterned electrode via the first through hole and the second through hole, and a second portion extending onto the common electrode. The common electrode is coupled with the patterned electrode to form a first storage capacitor and is coupled with the second portion to form a second storage capacitor.
    Type: Application
    Filed: August 14, 2013
    Publication date: December 5, 2013
    Applicant: AU Optronics Corp.
    Inventors: Chien-Chih Lee, Pei-Yi Shen, Ching-Yang Cheng, Shu-Ming Huang
  • Patent number: 8575612
    Abstract: The present invention provides a pixel structure including a substrate, a patterned electrode disposed on the substrate, a first insulating layer disposed on the patterned electrode, a common electrode disposed on the first insulating layer, a second insulating layer disposed on the common electrode, and a drain disposed on the second insulating layer. The first insulating layer has a first through hole, and the second insulating layer has a second through hole. The drain includes a first portion electrically connected to the patterned electrode via the first through hole and the second through hole, and a second portion extending onto the common electrode. The common electrode is coupled with the patterned electrode to form a first storage capacitor and is coupled with the second portion to form a second storage capacitor.
    Type: Grant
    Filed: May 2, 2012
    Date of Patent: November 5, 2013
    Assignee: AU Optronics Corp.
    Inventors: Chien-Chih Lee, Pei-Yi Shen, Ching-Yang Cheng, Shu-Ming Huang
  • Publication number: 20130015449
    Abstract: The present invention provides a pixel structure including a substrate, a patterned electrode disposed on the substrate, a first insulating layer disposed on the patterned electrode, a common electrode disposed on the first insulating layer, a second insulating layer disposed on the common electrode, and a drain disposed on the second insulating layer. The first insulating layer has a first through hole, and the second insulating layer has a second through hole. The drain includes a first portion electrically connected to the patterned electrode via the first through hole and the second through hole, and a second portion extending onto the common electrode. The common electrode is coupled with the patterned electrode to form a first storage capacitor and is coupled with the second portion to form a second storage capacitor.
    Type: Application
    Filed: May 2, 2012
    Publication date: January 17, 2013
    Inventors: Chien-Chih Lee, Pei-Yi Shen, Ching-Yang Cheng, Shu-Ming Huang
  • Patent number: 7304351
    Abstract: An active matrix substrate is provided, including a substrate, a plurality of pixel units, a static releasing conductive line and an ESD protection circuit, wherein the substrate has an active area and a peripheral area adjacent to each other. The pixel units are arranged in the active area in an array, and the static releasing conductive line is disposed in the peripheral area of the substrate. The ESD protection circuit is also disposed in the peripheral area of the substrate, being electrically connected between the pixel units and the static releasing conductive line. The ESD protection circuit includes a protection ring and a static consumption device, wherein the protection ring is disposed in a peripheral area of the substrate and the static consumption device has a floating gate, the static consumption device being electrically connected between the ESD protection circuit and the static releasing conductive line.
    Type: Grant
    Filed: September 18, 2005
    Date of Patent: December 4, 2007
    Assignee: Au Optronics Corporation
    Inventors: Po-Yuan Liu, Shu-Ming Huang, Chao-Liang Lu
  • Publication number: 20060278929
    Abstract: An active matrix substrate is provided, including a substrate, a plurality of pixel units, a static releasing conductive line and an ESD protection circuit, wherein the substrate has an active area and a peripheral area adjacent to each other. The pixel units are arranged in the active area in an array, and the static releasing conductive line is disposed in the peripheral area of the substrate. The ESD protection circuit is also disposed in the peripheral area of the substrate, being electrically connected between the pixel units and the static releasing conductive line. The ESD protection circuit includes a protection ring and a static consumption device, wherein the protection ring is disposed in a peripheral area of the substrate and the static consumption device has a floating gate, the static consumption device being electrically connected between the ESD protection circuit and the static releasing conductive line.
    Type: Application
    Filed: September 18, 2005
    Publication date: December 14, 2006
    Inventors: Po-Yuan Liu, Shu-Ming Huang, Chao-Liang Lu