Abstract: A processor includes a controller that measures an error rate of a signal that propagates through a communication line; switches to use a spare line to perform a first communication when a first error rate of a signal that propagates through a first communication line of a first line group exceeds a first threshold, the first communication being performed using the first communication line; and switches to use the first communication line to perform the first communication and switches to use the spare line to perform a second communication when the first communication is performed using the spare line, when a second error rate of a signal that propagates through a second communication line of a second line group exceeds a second threshold higher than the first threshold, and when the first error rate is lower than the second threshold; and a processor core that exchanges information via the controller.

Abstract: A processor includes a controller that measures an error rate of a signal that propagates through a communication line; switches to use a spare line to perform a first communication when a first error rate of a signal that propagates through a first communication line of a first line group exceeds a first threshold, the first communication being performed using the first communication line; and switches to use the first communication line to perform the first communication and switches to use the spare line to perform a second communication when the first communication is performed using the spare line, when a second error rate of a signal that propagates through a second communication line of a second line group exceeds a second threshold higher than the first threshold, and when the first error rate is lower than the second threshold; and a processor core that exchanges information via the controller.

Abstract: An information processing apparatus including: an arithmetic processing unit; and a communication device configured to receive data from another information processing apparatus through a plurality of first lanes and to output the received data to the arithmetic processing unit, wherein the communication device includes a detection unit that detects a failure of the plurality of first lanes; and a control unit that performs a first degradation process of stopping use of any one of the plurality of first lanes, based on a degradation request, performs a restoration process of resuming use of a first lane for which use has been stopped, based on a restoration request, and performs a second degradation process of stopping use of a first lane for which use has been resumed, when the detection unit detects a failure of the first lane for which use has been resumed, in the restoration process.

Abstract: An information processing apparatus includes: storage devices that store data; a data generation unit that generates padding-added data by adding padding to the data, based on adjustment information included in received data; and a storage processing unit that stores the padding-added data generated by the data generation unit in the storage devices. It is possible to shorten a latency even when non-aligned data is received.

Abstract: A communication apparatus includes a connection port and a processor. The connection port is connected to a switch apparatus. The processor is configured to acquire data to be transmitted to an external apparatus. The processor is configured to generate a packet destined to the external apparatus. The packet contains the data. The processor is configured to store the packet in a buffer. The processor is configured to acquire the packet from the buffer. The processor is configured to transmit the packet to the switch apparatus via the connection port. The processor is configured to acquire a state of a network to which the connection port is connected. The processor is configured to control, on basis of the state of the network and a predetermined packet generation time, a number of packets to be generated.

Abstract: An information processing device includes a transfer unit and an interface unit, the interface unit distributes transmission to a plurality of first lanes, and generate reception information from a plurality of pieces of distribution reception data received through a plurality of second lanes, the transfer unit includes a reception processing unit to extract reception data included in the reception information, and first error information indicating an error in any of the first lanes and a degeneration management unit to generate first degeneration information indicating a use stop lane among the first lanes, based on the first error information, generate second degeneration information indicating a use stop lane among the plurality of second lanes, based on second error information that is output from the interface unit, and cause the transmission processing unit to generate transmission information including the second degeneration information.

Abstract: A parallel computer includes a plurality of nodes. Each of the nodes includes a router directly or indirectly connected to each of the other nodes and a network interface connected to an external network of the parallel computer. The network interface includes a storage unit that holds detour route information indicating a detour route corresponding to a communication route from a node in which the network interface is included to another node. The network interface further includes a reception processing unit that, when the network interface receives data destined to one node of the parallel computer from the external network, sets detour route information corresponding to a communication route from the node in which the network interface is included to the destination node of the data for the data and transmits the data for which the detour route information is set to the destination node.

Abstract: A control method by an information processing system including a plurality of computers and a plurality of switch devices, the control method includes storing, by a first processor, degeneration information indicating a path in which a transmission rate is decreased and a decreasing ratio of a transmission rate in a first memory when a first switch device which include the first processor detects the path and the first switch device is set as a point of origin; determining, by a second processor, whether a plurality of packets pass through the path, based on the degeneration information when the plurality of packets are transmitted from a computer including the second processor; determining a length of a gap based on the decreasing ratio when it is determined that the plurality of packets pass through the path; and transmitting the plurality of packets with a transmission interval based on the length.

Abstract: An apparatus includes: a physical-layer device that distributes data to first lanes and performs data transfer to/from an external device by second lanes each of which has a number of the first lanes; and a transfer circuit that transfers data output by a central-processing unit performing arithmetic-processing to the physical-layer device and transfers the data received from the physical-layer device and received by the central-processing unit, the transfer circuit that comprises an information-acquisition unit that receives one of detection information of the first lanes which indicates that the physical-layer device has received data from the external device and error information of the first lanes which indicates that the data transferred to the physical-layer device from the external device has an error, from the physical-layer device, and a selection unit configured to specify the second lane to be degenerated based on one of the error information and the detection information.

Abstract: A parallel computer system includes information processing devices, each of the information processing devices including a communication control device that performs communication, a main memory that stores data, and an arithmetic processing device that is coupled to the communication control device and the main memory, the information processing devices being coupled to each other through a network by the respective communication control device, wherein the arithmetic processing device includes a cache memory and a cache controller, the cache controller that executes an atomic operation for target data on the cache memory that stores the target data when the communication control device outputs an atomic operation request that is used to request the atomic operation, the atomic operation being not divided into a smaller operation, and notifies the communication control device of a result that is obtained by executing the atomic operation on the cache memory.

Abstract: An information processing apparatus including: an arithmetic processing unit; and a communication device configured to receive data from another information processing apparatus through a plurality of first lanes and to output the received data to the arithmetic processing unit, wherein the communication device includes a detection unit that detects a failure of the plurality of first lanes; and a control unit that performs a first degradation process of stopping use of any one of the plurality of first lanes, based on a degradation request, performs a restoration process of resuming use of a first lane for which use has been stopped, based on a restoration request, and performs a second degradation process of stopping use of a first lane for which use has been resumed, when the detection unit detects a failure of the first lane for which use has been resumed, in the restoration process.

Abstract: A parallel computer system includes a plurality of processors including a first processor and a plurality of second processors; and a crossbar switch provided with a plurality of ports; wherein the first processor transmits data to a first port among the plurality of ports, and transmits standby time information to the first port in the case where the plurality of second processors are unable to transmit data to the first port despite receiving a communication authorization notification from the first port, and the first port receives the standby time information, and after the standby time elapses, selects one of the plurality of second processors.

Abstract: A switch includes a plurality of ports and a combination determining unit that determines a central processing unit (CPU) to be paired with one of the ports. The port includes: an arbitration circuit that selects the CPU to be paired therewith when receiving an arbitration request from the CPU to be paired in a predetermined state, and selects one of the CPUs from which the arbitration request has been received in other cases to return transmission permission; and a data transfer unit that transfers the received data from the selected CPU to another CPU. The CPU includes: a request transmission unit that transmits the arbitration request to the ports; and a data transmission unit that transmits data to the paired port when the arbitration request is transmitted to the paired port in the predetermined state, and transmits data to the ports that have returned transmission permission in other cases.

Abstract: A communication apparatus includes a connection port and a processor. The connection port is connected to a switch apparatus. The processor is configured to acquire data to be transmitted to an external apparatus. The processor is configured to generate a packet destined to the external apparatus. The packet contains the data. The processor is configured to store the packet in a buffer. The processor is configured to acquire the packet from the buffer. The processor is configured to transmit the packet to the switch apparatus via the connection port. The processor is configured to acquire a state of a network to which the connection port is connected. The processor is configured to control, on basis of the state of the network and a predetermined packet generation time, a number of packets to be generated.

Abstract: An information processing device includes a transfer unit and an interface unit, the interface unit distributes transmission to a plurality of first lanes, and generate reception information from a plurality of pieces of distribution reception data received through a plurality of second lanes, the transfer unit includes a reception processing unit to extract reception data included in the reception information, and first error information indicating an error in any of the first lanes and a degeneration management unit to generate first degeneration information indicating a use stop lane among the first lanes, based on the first error information, generate second degeneration information indicating a use stop lane among the plurality of second lanes, based on second error information that is output from the interface unit, and cause the transmission processing unit to generate transmission information including the second degeneration information.

Abstract: A storage system includes a plurality of control devices each including an interface unit and an arithmetic processing unit. The arithmetic processing unit stores, when requested to execute saving processing for saving dump data of a specific interface unit in which an error has occurred, the dump data collected from the specific interface unit into a storage unit. The arithmetic processing unit calculates an execution time of the saving processing. The arithmetic processing unit compresses, when the execution time exceeds a time limit and before a remaining time is reached, part of the dump data stored in the storage unit and save the compressed dump data into a saving unit. The arithmetic processing unit saves, when the execution time exceeds the time limit and after the remaining time has been reached, rest of the dump data stored in the storage unit into the saving unit without compression.

Abstract: With a command delay time measurement unit that issues a first test command while the medium error status generator generates the medium error status, and measures a delay time of a command response for the first test command as a command delay time, and a response interval measurement unit that issues a plurality of second test commands to the storage apparatuses to be examined under a higher load when no error occurs, and measures an interval of each command response for the plurality of second test commands as a response interval, and by calculating, for each of the plurality of types of the storage apparatuses, a reference time for each storage apparatus type by adding the command delay time and the response interval, an error can be detected more efficiently.

Abstract: An apparatus includes: a physical-layer device that distributes data to first lanes and performs data transfer to/from an external device by second lanes each of which has a number of the first lanes; and a transfer circuit that transfers data output by a central-processing unit performing arithmetic-processing to the physical-layer device and transfers the data received from the physical-layer device and received by the central-processing unit, the transfer circuit that comprises an information-acquisition unit that receives one of detection information of the first lanes which indicates that the physical-layer device has received data from the external device and error information of the first lanes which indicates that the data transferred to the physical-layer device from the external device has an error, from the physical-layer device, and a selection unit configured to specify the second lane to be degenerated based on one of the error information and the detection information.

Abstract: A storage system includes a plurality of control devices to control output and input of data to and from a storage device. At least one of the plurality of control devices includes an interface unit and an arithmetic processing unit. The interface unit receives an instruction regarding output or input of data to or from the storage device. The arithmetic processing unit receives the instruction from the interface unit and executes the instruction. The arithmetic processing unit selects, when an error has occurred in a specific interface unit, a first processing unit and requests the first processing unit to execute saving processing for saving dump data of the specific interface unit. The arithmetic processing unit selects, when a usage rate of the first processing unit goes beyond a threshold during execution of the saving processing, a second processing unit and requests the second processing unit to execute the saving processing.

Abstract: A control method by an information processing system including a plurality of computers and a plurality of switch devices, the control method includes storing, by a first processor, degeneration information indicating a path in which a transmission rate is decreased and a decreasing ratio of a transmission rate in a first memory when a first switch device which include the first processor detects the path and the first switch device is set as a point of origin; determining, by a second processor, whether a plurality of packets pass through the path, based on the degeneration information when the plurality of packets are transmitted from a computer including the second processor; determining a length of a gap based on the decreasing ratio when it is determined that the plurality of packets pass through the path; and transmitting the plurality of packets with a transmission interval based on the length.