Abstract: A circuit for controlling a latch mode of a pulse width modulation circuit includes a D flip-flop, a voltage generation unit, a comparator, and a logic unit. The D flip-flop generates a switch control signal according to a latch enable signal. The voltage generation unit generates a discharge current, and a voltage divider resistor group included in the voltage generation unit generates a first voltage when the voltage generation unit is turned on according to the switch control signal. A voltage of a predetermined pin of the pulse width modulation circuit is equal to a predetermined voltage when the discharge current is equal to the charge current. The comparator compares a reference voltage with the first voltage to generate a comparison signal. The logic unit generates a clear signal according to the comparison signal. The D flip-flop clears the switch control signal according to the clear signal.

Abstract: Disclosure includes a control method for over voltage protection, suitable for a power converter. The power converter has a rectifier for rectifying an alternative-current voltage into a direct-current input voltage. The direct-current input voltage is sensed and determined whether it locates in a valley. A detection voltage is provided, capable of representing the direct-current input voltage. The detection voltage is compared with a predetermined reference voltage. When the detection voltage exceeds the predetermined reference voltage and the direct-current input voltage is in the valley, an OVP signal is provided to stop the power conversion of the power converter.

Abstract: Disclosure includes a control method for over voltage protection, suitable for a power converter. The power converter has a rectifier for rectifying an alternative-current voltage into a direct-current input voltage. The direct-current input voltage is sensed and determined whether it locates in a valley. A detection voltage is provided, capable of representing the direct-current input voltage. The detection voltage is compared with a predetermined reference voltage. When the detection voltage exceeds the predetermined reference voltage and the direct-current input voltage is in the valley, an OVP signal is provided to stop the power conversion of the power converter.

Abstract: Power control circuits and methods are disclosed, suitable for a power supplier. A power control circuit has a clock generator, a phase controller and a power limiter. The clock generator provides a clock signal, substantially determining switching cycles of a power supply. The phase controller outputs a burst signal based on a group reference signal and a burst initiation signal, and makes a burst period corresponding to a burst signal not less than a group reference period corresponding to the group reference signal. The burst signal is capable of switching the power supplier between a switching state and a non-switching state. The power limiter limits the power transferred by the power supply in every switching cycle, during a burst-up duration after the power supply is switched from the non-switching state to the switching state. The burst initiation signal correlates to an output voltage of the power supplier.

Abstract: A circuit for controlling a latch mode of a pulse width modulation circuit includes a D flip-flop, a voltage generation unit, a comparator, and a logic unit. The D flip-flop generates a switch control signal according to a latch enable signal. The voltage generation unit generates a discharge current, and a voltage divider resistor group included in the voltage generation unit generates a first voltage when the voltage generation unit is turned on according to the switch control signal. A voltage of a predetermined pin of the pulse width modulation circuit is equal to a predetermined voltage when the discharge current is equal to the charge current. The comparator compares a reference voltage with the first voltage to generate a comparison signal. The logic unit generates a clear signal according to the comparison signal. The D flip-flop clears the switch control signal according to the clear signal.

Abstract: A circuit for discharging an X capacitor includes an AC detection unit, a reset unit, a counter, and a discharging unit. The AC detection unit is coupled to two terminals of the X capacitor through a pin. The AC detection unit has a plurality of reference levels for detecting a DC voltage level according to the plurality of reference levels, and outputting a detection signal. The reset unit is coupled to the AC detection unit for generating a reset signal according to the detection signal. The counter is coupled to the reset unit for being reset according to the reset signal. When the counter does not receive the reset signal within a first predetermined time, the counter generates a turning-on signal. The discharging unit is coupled to the counter for discharging the X capacitor according to the turning-on signal.