Patents by Inventor Shun-Fa Feng

Shun-Fa Feng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8022402
    Abstract: An active device array substrate including a substrate, a pixel array, and peripheral circuit is provided. The substrate has a display region and a peripheral region. The pixel array is disposed on the display region of the substrate, wherein the pixel array includes signal lines and pixels, each of the pixels is electrically connected to the signal lines respectively and extends from the display region to the peripheral region. The peripheral circuit is disposed on the peripheral region and includes a testing circuit electrically connected to the signal lines. Additionally, the testing circuit includes shorting bars and connecting conductors, wherein each of the signal lines is electrically connected to one of the shorting bars through one of the connecting connectors respectively, and at least two of the signal lines connected to the same shorting bar are electrically connected to each other through one of the connecting conductors.
    Type: Grant
    Filed: December 24, 2008
    Date of Patent: September 20, 2011
    Assignee: Au Optronics Corporation
    Inventors: Jen-Chieh Li, Shun-Fa Feng
  • Publication number: 20100140615
    Abstract: An active device array substrate including a substrate, a pixel array, and peripheral circuit is provided. The substrate has a display region and a peripheral region. The pixel array is disposed on the display region of the substrate, wherein the pixel array includes signal lines and pixels, each of the pixels is electrically connected to the signal lines respectively and extends from the display region to the peripheral region. The peripheral circuit is disposed on the peripheral region and includes a testing circuit electrically connected to the signal lines. Additionally, the testing circuit includes shorting bars and connecting conductors, wherein each of the signal lines is electrically connected to one of the shorting bars through one of the connecting connectors respectively, and at least two of the signal lines connected to the same shorting bar are electrically connected to each other through one of the connecting conductors.
    Type: Application
    Filed: December 24, 2008
    Publication date: June 10, 2010
    Applicant: AU OPTRONICS CORPORATION
    Inventors: Jen-Chieh Li, Shun-Fa Feng
  • Publication number: 20100051335
    Abstract: A conducting layer jump connection structure used in a circuit device includes a substrate, a first conducting layer, a first insulating layer, a second conducting layer, a second insulating layer, a jump connection layer, a first via, and plural second vias. The first conducting layer covers the substrate. The first insulating layer covers the first conducting layer. The second conducting layer partially covers the first insulating layer. The second insulating layer covers the second conducting layer and the first insulating layer exposed by the second conducting layer. The jump connection layer covers the second insulating layer. The first via is formed on the first conducting layer and between two opposite second conducting portions of the second conducting layer. The first via penetrates through both the second insulating layer and the first insulating layer. The second vias are formed on the second conducting layer and penetrate through the second insulating layer.
    Type: Application
    Filed: August 31, 2009
    Publication date: March 4, 2010
    Applicant: AU Optronics Corporation
    Inventors: Chien-Li Chen, Shun-Fa Feng, Yan-Lin Yeh