Patents by Inventor Shun Hao
Shun Hao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11961919Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate, where a top portion of the fin comprises a layer stack that includes alternating layers of a first semiconductor material and a second semiconductor material; forming a dummy gate structure over the fin; forming openings in the fin on opposing sides of the dummy gate structure; forming source/drain regions in the openings; removing the dummy gate structure to expose the first semiconductor material and the second semiconductor material under the dummy gate structure; performing a first etching process to selectively remove the exposed first semiconductor material, where after the first etching process, the exposed second semiconductor material form nanostructures, where each of the nanostructures has a first shape; and after the first etching process, performing a second etching process to reshape each of the nanostructures into a second shape different from the first shape.Type: GrantFiled: March 21, 2022Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Chung Chang, Hsiu-Hao Tsao, Ming-Jhe Sie, Shun-Hui Yang, Chen-Huang Huang, An Chyi Wei, Ryan Chia-Jen Chen
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Publication number: 20240107656Abstract: A circuit board assembly is applied to the field of electronic communications technologies to resolve a prior-art heat dissipation problem of a circuit board. The circuit board assembly combines, on a second circuit board, low-speed signals transmitted between a plurality of I/O modules and an IC chip, and then transmits the combined low-speed signals to the IC chip by using a low-speed cable. A low-speed signal sent by the IC chip to the plurality of I/O modules is extended to a plurality of low-speed signals on the second circuit board, and then the plurality of low-speed signals are separately sent to the plurality of I/O modules. This may be applied to a scenario in which a relatively large quantity of electronic components need to be disposed on a circuit board.Type: ApplicationFiled: September 26, 2023Publication date: March 28, 2024Inventors: Chaojun DENG, Fei MA, Wei FANG, Zhiwen YANG, Chungang LI, Shun HAO
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Patent number: 11805592Abstract: A circuit board assembly is applied to the field of electronic communications technologies to resolve a prior-art heat dissipation problem of a circuit board. The circuit board assembly combines, on a second circuit board, low-speed signals transmitted between a plurality of I/O modules and an IC chip, and then transmits the combined low-speed signals to the IC chip by using a low-speed cable. A low-speed signal sent by the IC chip to the plurality of I/O modules is extended to a plurality of low-speed signals on the second circuit board, and then the plurality of low-speed signals are separately sent to the plurality of I/O modules. This may be applied to a scenario in which a relatively large quantity of electronic components need to be disposed on a circuit board.Type: GrantFiled: January 22, 2021Date of Patent: October 31, 2023Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Chaojun Deng, Fei Ma, Wei Fang, Zhiwen Yang, Chungang Li, Shun Hao
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Patent number: 11232056Abstract: There is disclosed in an example, an endpoint apparatus for an interconnect, comprising: a mechanical and electrical interface to the interconnect; and one or more logic elements comprising an interface vector engine to: receive a first scalar transaction for the interface; determine that the first scalar transaction meets a criterion for vectorization; receive a second scalar transaction for the interface; determine that the second transaction meets the criterion for vectorization; vectorize the first scalar transaction and second scalar transaction into a vector transaction; and send the vector transaction via the electrical interface.Type: GrantFiled: December 28, 2016Date of Patent: January 25, 2022Assignee: Intel CorporationInventors: Wenqian Yu, Cunming Liang, Ping Yu, Shun Hao, Helin Zhang
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Patent number: 11145662Abstract: A memory structure including a substrate, a first transistor, a second transistor, and a trench capacitor is provided. The trench capacitor is disposed in the substrate and is connected between the first transistor and the second transistor.Type: GrantFiled: July 31, 2020Date of Patent: October 12, 2021Assignee: Powerchip Semiconductor Manufacturing CorporationInventor: Shun-Hao Chao
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Publication number: 20210212193Abstract: A circuit board assembly is applied to the field of electronic communications technologies to resolve a prior-art heat dissipation problem of a circuit board. The circuit board assembly combines, on a second circuit board, low-speed signals transmitted between a plurality of I/O modules and an IC chip, and then transmits the combined low-speed signals to the IC chip by using a low-speed cable. A low-speed signal sent by the IC chip to the plurality of I/O modules is extended to a plurality of low-speed signals on the second circuit board, and then the plurality of low-speed signals are separately sent to the plurality of I/O modules. This may be applied to a scenario in which a relatively large quantity of electronic components need to be disposed on a circuit board.Type: ApplicationFiled: January 22, 2021Publication date: July 8, 2021Inventors: Chaojun DENG, Fei MA, Wei FANG, Zhiwen YANG, Chungang LI, Shun HAO
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Publication number: 20200365600Abstract: A memory structure including a substrate, a first transistor, a second transistor, and a trench capacitor is provided. The trench capacitor is disposed in the substrate and is connected between the first transistor and the second transistor.Type: ApplicationFiled: July 31, 2020Publication date: November 19, 2020Applicant: Powerchip Semiconductor Manufacturing CorporationInventor: Shun-Hao Chao
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Publication number: 20200301861Abstract: There is disclosed in an example, an endpoint apparatus for an interconnect, comprising: a mechanical and electrical interface to the interconnect; and one or more logic elements comprising an interface vector engine to: receive a first scalar transaction for the interface; determine that the first scalar transaction meets a criterion for vectorization; receive a second scalar transaction for the interface; determine that the second transaction meets the criterion for vectorization; vectorize the first scalar transaction and second scalar transaction into a vector transaction; and send the vector transaction via the electrical interfaceType: ApplicationFiled: December 28, 2016Publication date: September 24, 2020Applicant: Intel CorporationInventors: Wenqian Yu, Cunming Liang, Ping Yu, Shun Hao, Helin Zhang
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Patent number: 10784267Abstract: A memory structure including a substrate, a first transistor, a second transistor, and a trench capacitor is provided. The trench capacitor is disposed in the substrate and is connected between the first transistor and the second transistor.Type: GrantFiled: June 19, 2019Date of Patent: September 22, 2020Assignee: Powerchip Semiconductor Manufacturing CorporationInventor: Shun-Hao Chao
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Patent number: 9949170Abstract: Techniques for modifying a transmission rate of a device having a plurality of transmission rate options are described herein. The techniques include a method comprising receiving data from a sensor indicating movement of an electronic device, the electronic device having a plurality of transmission rate options. Fail ratio metrics are gathered. The fail ratio metrics indicate a ratio of failed transmissions to successful transmissions for rate option during device movement. The method includes determining whether a given rate option has a fail ratio above a predetermined threshold; and, if so, disabling the given rate option while the device is moving.Type: GrantFiled: November 1, 2013Date of Patent: April 17, 2018Assignee: Intel CorporationInventors: Shun Hao, Ren Wang, Jr-Shian Tsai, Alexander Min, Roi Sadan, Jianghong Du, Arvind Kumar, Liraz Zur, Longcheng Zhu
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Publication number: 20160227442Abstract: Techniques for modifying a transmission rate of a device having a plurality of transmission rate options are described herein. The techniques include a method comprising receiving data from a sensor indicating movement of an electronic device, the electronic device having a plurality of transmission rate options. Fail ratio metrics are gathered. The fail ratio metrics indicate a ratio of failed transmissions to successful transmissions for rate option during device movement. The method includes determining whether a given rate option has a fail ratio above a predetermined threshold; and, if so, disabling the given rate option while the device is moving.Type: ApplicationFiled: November 1, 2013Publication date: August 4, 2016Applicant: Intel CorporationInventors: Shun Hao, Ren Wang, Jr-Shian Tsai, Alexander Min, Roi Sadan, Jianghong Du, Arvind Kumar, Liraz Zur, Longcheng Zhu
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Patent number: 6153936Abstract: A method for manufacturing a semiconductor structure having a via hole is provided. The method includes steps of providing a base, forming a pad on the base, forming a device on the pad, forming a dielectric layer over the device and the base, executing a planarization process with etch back, and etching the dielectric layer to form the via hole. The manufactured semiconductor structure has a dielectric layer having therein the via hole, a device under the dielectrc layer, and a pad under the device for raising the device. The method and structure can prevent a residue due to planarization process from being remained between the dielectric layer and the device.Type: GrantFiled: July 31, 1998Date of Patent: November 28, 2000Assignee: Winbond Electronics, Corp.Inventor: Shun-Hao Chao