Patents by Inventor Shun-Hao Chao

Shun-Hao Chao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory structure
    Patent number: 11145662
    Abstract: A memory structure including a substrate, a first transistor, a second transistor, and a trench capacitor is provided. The trench capacitor is disposed in the substrate and is connected between the first transistor and the second transistor.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: October 12, 2021
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventor: Shun-Hao Chao
  • MEMORY STRUCTURE
    Publication number: 20200365600
    Abstract: A memory structure including a substrate, a first transistor, a second transistor, and a trench capacitor is provided. The trench capacitor is disposed in the substrate and is connected between the first transistor and the second transistor.
    Type: Application
    Filed: July 31, 2020
    Publication date: November 19, 2020
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventor: Shun-Hao Chao
  • Memory structure
    Patent number: 10784267
    Abstract: A memory structure including a substrate, a first transistor, a second transistor, and a trench capacitor is provided. The trench capacitor is disposed in the substrate and is connected between the first transistor and the second transistor.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: September 22, 2020
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventor: Shun-Hao Chao
  • Method for forming via hole and semiconductor structure formed thereby
    Patent number: 6153936
    Abstract: A method for manufacturing a semiconductor structure having a via hole is provided. The method includes steps of providing a base, forming a pad on the base, forming a device on the pad, forming a dielectric layer over the device and the base, executing a planarization process with etch back, and etching the dielectric layer to form the via hole. The manufactured semiconductor structure has a dielectric layer having therein the via hole, a device under the dielectrc layer, and a pad under the device for raising the device. The method and structure can prevent a residue due to planarization process from being remained between the dielectric layer and the device.
    Type: Grant
    Filed: July 31, 1998
    Date of Patent: November 28, 2000
    Assignee: Winbond Electronics, Corp.
    Inventor: Shun-Hao Chao