Patents by Inventor Shun-Ho Lin

Shun-Ho Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200097057
    Abstract: A server rack includes a plurality of servers, each of which includes: a power management unit operable to convert a DC input voltage into at least one DC output voltage to output at least one type of DC output power; at least one application circuit for being respectively powered by the at least one type of DC output power; and a baseboard management controller cooperating with the power management unit to provide power management data. One of the baseboard management controllers of the servers is for receiving the power management data respectively from the other one(s) of the baseboard management controllers, and controls the power management units of the servers for power management of the servers based on the power management data.
    Type: Application
    Filed: July 30, 2019
    Publication date: March 26, 2020
    Inventors: Chia-Hung TSENG, Han-Ching HSIEH, Kuan-Ho LIN, Shun-Chi LEE
  • Patent number: 5480837
    Abstract: An improved process for fabricating an integrated circuit is achieved by forming a planar conductive layer over closely spaced structures, such as gate electrode structures of field effect transistors (FET) and the electrically interconnecting word line structures of DRAM and SRAM chips. The planar conductive layer is then patterned by plasma etching to form the next level of electrical interconnecting bit lines, which makes contact to the source/drain of the FETs. The process involves the conformal deposition of a relatively thick polysilicon layer to fill the submicrometer spaces in the underlying structure. An etch back of the polysilicon and the deposition of a metal silicide is used to form an essentially planar conducting layer. This locally planar layer over submicrometer spaced features, with high aspect ratios, provides an ideal surface for exposing and developing distortion free and residue free submicrometer photoresist images required for Ultra Large Semiconductor Integration (ULSI).
    Type: Grant
    Filed: June 27, 1994
    Date of Patent: January 2, 1996
    Assignee: Industrial Technology Research Institute
    Inventors: Ing-Ruey Liaw, Shun-Ho Lin