Abstract: A system for manufacturing an integrated circuit includes a processor coupled to a non-transitory computer readable medium configured to store executable instructions. The processor is configured to execute the instructions for generating a layout design of the integrated circuit that has a set of design rules. The generating of the layout design includes generating a set of gate layout patterns corresponding to fabricating a set of gate structures of the integrated circuit, generating a cut feature layout pattern corresponding to a cut region of a first gate of the set of gate structures of the integrated circuit, generating a first conductive feature layout pattern corresponding to fabricating a first conductive structure of the integrated circuit, and generating a first via layout pattern corresponding to a first via. The cut feature layout pattern overlaps a first gate layout pattern of the set of gate layout patterns.

Abstract: A structure applied to a photolithographic process is provided. The structure includes at least a film layer, an optical isolation layer, an anti-reflection coating and a photoresist layer sequentially formed over a substrate. In the photolithographic process, the optical isolation layer stops light from penetrating down to the film layer. Since the optical isolation layer is set up underneath the photoresist layer, light emitted from a light source during photo-exposure is prevented from reflecting from the substrate surface after passing through the film layer. Thus, the critical dimensions of the photolithographic process are unaffected by any change in the thickness of the film layer.

Abstract: A method for analyzing overlay errors in lithography is described. Interfield sampling and intrafield sampling are first conducted to sample multiple positions on each of the wafers, and then the overlay error value at each of the positions is measured. An overlay error model including coefficients of intrafield and interfield overlay errors of different types is used to fit the measured overlay error values with respect to the sampled positions. In the overlay error model, the intrafield overlay errors include intrafield translation, isotropic magnification, reticle rotation, asymmetric magnification and asymmetric rotation, and the interfield overlay errors include interfield translation, scale error, wafer rotation and orthogonality error.

Abstract: A photoresist with adjustable polarized light response and a photolithography process using the photoresist. The photoresist and the photolithography process are suitable for use in an exposure optical system with a high numerical aperture. The photoresist includes a photosensitive polymer that can absorb the exposure light source to generate an optical reaction. The photosensitive polymer can also be oriented along a direction of an electric field or a magnetic field. The response for the photosensitive upon a polarized light is determined by an angle between the predetermined direction and the polarized light. In addition, the photolithography process adjusts the orientation of the photosensitive polymer, so that the P-polarized light has a weaker response than that of the S-polarized light to compensate for the larger transmission coefficient of the P-polarized light with a high numerical aperture, so as to prevent the photoresist pattern deformation.

Abstract: A method of code programming a mask read only memory (ROM) is disclosed. A method of the present invention includes forming a layer of developable anti-reflective coating over a plurality of code openings located on a substrate of a ROM device. The plurality of code openings are typically elements of a first code, or pre-code, pattern, and a portion of the developable anti-reflective coating layer is removed or processed to define a second code, or real-code, pattern of the device. The method may be practiced by applying and patterning a layer of photoresist material over the developable anti-reflective coating to form a second code pattern, and then removing portions of the developable anti-reflective coating that remain exposed beneath the patterned photoresist material.

Abstract: A method for analyzing overlay errors in lithography is described. Interfield sampling and intrafield sampling are first conducted to sample multiple positions on each of the wafers, and then the overlay error value at each of the positions is measured. An overlay error model including coefficients of intrafield and interfield overlay errors of different types is used to fit the measured overlay error values with respect to the sampled positions. In the overlay error model, the intrafield overlay errors include intrafield translation, isotropic magnification, reticle rotation, asymmetric magnification and asymmetric rotation, and the interfield overlay errors include interfield translation, scale error, wafer rotation and orthogonality error.

Abstract: A structure applied to a photolithographic process is provided. The structure includes at least a film layer, an optical isolation layer, an anti-reflection coating and a photoresist layer sequentially formed over a substrate. In the photolithographic process, the optical isolation layer stops light from penetrating down to the film layer. Since the optical isolation layer is set up underneath the photoresist layer, light emitted from a light source during photo-exposure is prevented from reflecting from the substrate surface after passing through the film layer. Thus, the critical dimensions of the photolithographic process are unaffected by any change in the thickness of the film layer.

Abstract: A structure applied to a photolithographic process is provided. The structure comprises at least a film layer, an optical isolation layer, an anti-reflection coating and a photoresist layer sequentially formed over a substrate. In the photolithographic process, the optical isolation layer stops light from penetrating down to the film layer. Since the optical isolation layer is set up underneath the photoresist layer, light emitted from a light source during photo-exposure is prevented from reflecting from the substrate surface after passing through the film layer. Thus, the critical dimensions of the photolithographic process are unaffected by any change in the thickness of the film layer.

Abstract: In the manufacturing of VLSI circuits, production of overlay is a critical step. To obtain a higher resolution and alignment accuracy in microlithographic process, overlay errors must be measured so that overlay errors can be reduced to a tolerable level. This invention provides an overlay error model and a sampling strategy. Utilizing the overlay model and sampling strategy, a device for measuring overlay errors is also designed.

Abstract: A mask with extended mask window for forming patterns on a semiconductor substrate. The mask includes a main chip array having four sides for forming patterns of a main chip in a semiconductor substrate and a plurality of extended mask windows arranged around the main chip array. A method of dummy exposure using the mask includes providing a semiconductor substrate comprising a nitride layer with a plurality of main chip areas therein, and a plurality of unpatterned areas therein, forming a resist layer on the semiconductor substrate, providing an exposure mask comprising a main chip array and a plurality of extended mask windows, patterning the main chip areas of the semiconductor substrate using the main chip array of the exposure mask, patterning the unpatterned areas of the semiconductor substrate using the windows of the exposure mask, and removing the unexposed portions of the resist layer.

Abstract: A structure applied to a photolithographic process is provided. The structure comprises at least a film layer, an optical isolation layer, an anti-reflection coating and a photoresist layer sequentially formed over a substrate. In the photolithographic process, the optical isolation layer stops light from penetrating down to the film layer. Since the optical isolation layer is set up underneath the photoresist layer, light emitted from a light source during photo-exposure is prevented from reflecting from the substrate surface after passing through the film layer. Thus, the critical dimensions of the photolithographic process are unaffected by any change in the thickness of the film layer.

Abstract: A template padding method for padding edges of at least one hole on a semiconductor mask. The exposure and padding process is modulized. A padding database is developed based on the feature size and the pattern to be exposed. In the method of the present invention, the environment to be exposed is found firstly, and specific exposure module is then searched out. The padding result of the module is pre-found and stored in a database by diffraction operation, such as OPC method. Padding of a hole on a mask about a cell of a wafer can be performed directly by using a value stored. The complicated calculation can be greatly reduced. The method is adjustable according to the feature size of the product and the exposing pattern. The method can be used to random-distribution of holes on a mask surface, so as to determine a padding area effectively.

Abstract: A photoresist with adjustable polarized light response and a photolithography process using the photoresist. The photoresist and the photolithography process are suitable for use in an exposure optical system with a high numerical aperture. The photoresist includes a photosensitive polymer that can absorb the exposure light source to generate an optical reaction. The photosensitive polymer can also be oriented along a direction of an electric field or a magnetic field. The response for the photosensitive upon a polarized light is determined by an angle between the predetermined direction and the polarized light. In addition, the photolithography process adjusts the orientation of the photosensitive polymer, so that the P-polarized light has a weaker response than that of the S-polarized light to compensate for the larger transmission coefficient of the P-polarized light with a high numerical aperture, so as to prevent the photoresist pattern deformation.

Abstract: A mask with extended mask window for forming patterns on a semiconductor substrate. The mask includes a main chip array having four sides for forming patterns of a main chip in a semiconductor substrate and a plurality of extended mask windows arranged around the main chip array. A method of dummy exposure using the mask includes providing a semiconductor substrate comprising a nitride layer with a plurality of main chip areas therein, and a plurality of unpatterned areas therein, forming a resist layer on the semiconductor substrate, providing an exposure mask comprising a main chip array and a plurality of extended mask windows, patterning the main chip areas of the semiconductor substrate using the main chip array of the exposure mask, patterning the unpatterned areas of the semiconductor substrate using the windows of the exposure mask, and removing the unexposed portions of the resist layer.

Abstract: A method of optical proximity correction, suitably applied to a photolithography process with a high numeric aperture. The exposure light comprises a P-polarized light and an S-polarized light perpendicular to the P-polarized light. The P-polarized light has a transmission coefficient larger than that of the S-polarized light. In this method, different optical proximity correction modes are applied to the patterns with different orientations. While correcting any pattern, the ratio of transmission coefficient of the P-polarized light to the S-polarized light and the polarization angle between the pattern orientation and the polarization direction of the P-polarization/S-polarization light are considered.

Abstract: A method for fabricating a MOSFET structure having a source/drain extension and a source/drain region is disclosed, in which a basic antireflection coating is formed over a semiconductor substrate. A photoresist layer is formed over the basic antireflection coating. The photoresist layer is exposed to a radiation for transferring a pattern on the photoresist layer and the exposed photoresist layer is developed to form an opening over the areas for forming the source/drain regions, as a result a photoresist pattern with footing structures at a bottom comer of the photoresist pattern is formed. An ion implantation using the photoresist pattern as a mask, to simultaneously to form a source/drain extension and a source/drain region.

Abstract: The invention provides a method for reducing roughness of the photoresist through cross-linking reaction of deposit and the photoresist. The method comprises at least performing an exposure process to a substrate having a photoresist pattern and performing a post-exposure bake process for activating the surface of photoresist pattern. A material layer is formed to cover the surface of the photoresist pattern. The material layer cross-links with the hydrogen ions on the surface of the photoresist pattern, so that a filling layer is formed to fills asperity or the rough regions of the photoresist pattern.

Abstract: Forming a patterned photoresist over the substrate, herein numerous ions are formed during the formation of the patterned photoresist. Treat the patterned photoresist to increase the ions density at the top of the patterned photoresist. Cover the patterned photoresist by a reactive layer, wherein the reaction between the reactive layer and the ions forms a crosslinked layer over the surface of the patterned photoresist. And remove non-crosslinked portions of the reactive layer. Moreover, the treatment of the patterned photoresist could be heat the pattered photoresist or illuminate the patterned photoresist. Besides, the treatment also could be performed after the reactive layer is covered.

Abstract: A photoresist layer comprising an optically active component is provided, so that after an incident linearly polarized light penetrates the photoresist layer, the intensity ratio of an S wave polarization and a P wave polarization divided from the linearly polarized light is effectively 1:1 so improving astigmatism.

Abstract: An optical proximity correction method for producing a rectangular contact. The method includes representing the rectangular contact pattern required by an integrated circuit by a pair of connected hammerhead patterns and serif patterns at the inner straight corners of the hammerhead patterns. By varying the width of the connecting section of the hammerhead patterns, an optimal aspect ratio for the rectangular pattern is obtained.