Patents by Inventor Shun-Lin Su

Shun-Lin Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method to adaptively calculate resistor mesh in IC designs
    Patent number: 8984468
    Abstract: Using an adaptive square mesh for parasitic extraction, small squares of a predetermined minimum size will be placed where accuracy in the parasitic calculations is most critical—around edges, contacts and vias, and corners. Then, in areas where the parasitic analysis is less critical, for example in open spaces, a more coarse grid consisting of larger squares may be used to calculate the parasitic values in those spaces. Squares in the mesh may increase in size gradually to provide more accurate results.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: March 17, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Shun-Lin Su, Yue-Zhong Shu, Chi-Yuan Lo
  • Method of compressing data for use in performing VLSI mask layout verification
    Patent number: 5613102
    Abstract: A method of compressing data used in integrated circuit (IC) layout verifications includes the steps of identifying each circuit component from each layer of the IC chip; sorting each circuit component in an established order; identifying predetermined parameters for each component; determining the difference in value of the parameters for each pair of components in successive order; and storing the difference values for each pair of components.
    Type: Grant
    Filed: October 19, 1995
    Date of Patent: March 18, 1997
    Assignee: Lucent Technologies Inc.
    Inventors: Kuang-Wei Chiang, Chi-Yuan Lo, Doowan Paik, Shun-Lin Su