Patents by Inventor Shun Long Chen

Shun Long Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6818533
    Abstract: Within a plasma enhanced chemical vapor deposition (PECVD) method for forming within a microelectronic fabrication an epitaxial semiconductor layer comprising at least one of silicon and germanium, there is employed a reactant gas composition comprising: (1) at least one of a silicon source material and a germanium source material; and (2) an inert carrier gas. The inert carrier gas provides the epitaxial semiconductor layer with attenuated defects.
    Type: Grant
    Filed: May 9, 2002
    Date of Patent: November 16, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Sheng-Hsiung Chen, Shun Long Chen, Hungtse Lin, Ming Shing Tsai, Lan-Chieh Shih
  • Patent number: 6730580
    Abstract: Within a Czochralski method for fabricating a silicon substrate wafer which employs pulling a silicon monocrystal ingot from a silicon melt and slicing therefrom the silicon substrate wafer, at least one of: (1) the silicon melt has introduced therein a halogen getter material from an extrinsic source; and (2) the silicon substrate wafer is further treated with a plasma. In accord with the method, the silicon substrate wafer is provided with attenuated defects.
    Type: Grant
    Filed: July 3, 2001
    Date of Patent: May 4, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Hsiung Chen, Shun-Long Chen, Hungtse Lin, Naite Chen
  • Publication number: 20030211712
    Abstract: Within a plasma enhanced chemical vapor deposition (PECVD) method for forming within a microelectronic fabrication an epitaxial semiconductor layer comprising at least one of silicon and germanium, there is employed a reactant gas composition comprising: (1) at least one of a silicon source material and a germanium source material; and (2) an inert carrier gas. The inert carrier gas provides the epitaxial semiconductor layer with attenuated defects.
    Type: Application
    Filed: May 9, 2002
    Publication date: November 13, 2003
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Hsiung Chen, Shun Long Chen, Hungtse Lin, Ming Shing Tsai, Lan-Chieh Shih
  • Patent number: 6560862
    Abstract: A method to fabricate a bonding pad structure including the following steps. A substrate having a top metal layer and a passivation layer overlying the top metal layer is provided. The top metal layer being electrically connected to a lower metal layer by at least one metal via within a metal via area. The substrate includes a low-k dielectric layer at least between the lower metal layer and the top metal layer. The passivation layer is etched within the metal via area to form a trench exposing at least a portion of the top metal layer. A patterned, extended bonding pad is formed over the etched passivation layer and lining the trench. The extended bonding pad having a portion that extends over a peripheral planar area of the substrate adjacent the trench not within the metal via area. A wire bond is bonded to the extended bonding pad at the peripheral planar area portion to form the bonding pad structure.
    Type: Grant
    Filed: February 6, 2001
    Date of Patent: May 13, 2003
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Sheng-Hsiung Chen, Shun Long Chen, Hungtse Lin
  • Publication number: 20030074789
    Abstract: A method to fabricate a bonding pad structure including the following steps. A substrate having a top metal layer and a passivation layer overlying the top metal layer is provided. The top metal layer being electrically connected to a lower metal layer by at least one metal via within a metal via area. The substrate includes a low-k dielectric layer at least between the lower metal layer and the top metal layer. The passivation layer is etched within the metal via area to form a trench exposing at least a portion of the top metal layer. A patterned, extended bonding pad is formed over the etched passivation layer and lining the trench. The extended bonding pad having a portion that extends over a peripheral planar area of the substrate adjacent the trench not within the metal via area. A wire bond is bonded to the extended bonding pad at the peripheral planar area portion to form the bonding pad structure.
    Type: Application
    Filed: February 6, 2001
    Publication date: April 24, 2003
    Applicant: Taiwan Semiconductor Manufacturing Company
    Inventors: Sheng-Hsiung Chen, Shun Long Chen, Hungtse Lin
  • Patent number: 6518166
    Abstract: A process for forming a dual damascene opening, in a composite layer comprised with low k layers, to accommodate a dual damascene type, copper structure, has been developed. The process features the use of a silicon oxide layer, formed on the surfaces of the composite layer, exposed in the narrow diameter, via hole component of the dual damascene opening. The silicon oxide layer prevents via poisoning, or outgassing of amines or hydroxyls from the low k layers exposed in the via hole opening, that can evolve during a subsequent photolithographic development cycle, used to define the trench shape component of the dual damascene opening. The protective silicon oxide layer is conformally formed on the exposed-surfaces of the via hole component, via a liquid phase deposition procedure, performed at room temperature.
    Type: Grant
    Filed: April 23, 2001
    Date of Patent: February 11, 2003
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Sheng Hsiung Chen, Shun Long Chen, Hungtse Lin, Frank Hsu, Tsu Shih
  • Publication number: 20030008479
    Abstract: Within a Czochralski method for fabricating a silicon substrate wafer which employs pulling a silicon monocrystal ingot from a silicon melt and slicing therefrom the silicon substrate wafer, at least one of: (1) the silicon melt has introduced therein a halogen getter material from an extrinsic source; and (2) the silicon substrate wafer is further treated with a plasma. In accord with the method, the silicon substrate wafer is provided with attenuated defects.
    Type: Application
    Filed: July 3, 2001
    Publication date: January 9, 2003
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Hsiung Chen, Shun-Long Chen, Hungtse Lin, Naite Chen
  • Patent number: 5933229
    Abstract: A method for optically inspecting a semiconductor substrate for defects such as oxidation induced stacking faults, and a template mask which assists in practicing the optical inspection method. There is first provided a semiconductor substrate which has a surface to be inspected for defects such as oxidation induced stacking faults. Aligned then upon the surface of the semiconductor substrate to be inspected for defects such as oxidation induced stacking faults is a template mask. The template mask has a minimum of one aperture which leaves exposed a portion of the surface of the semiconductor substrate to be inspected for defects such as oxidation induced stacking faults. Finally, there is inspected optically the portion of the surface of the semiconductor substrate exposed through the aperture.
    Type: Grant
    Filed: September 10, 1997
    Date of Patent: August 3, 1999
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Ching Hua Yeh, Shun-Long Chen
  • Patent number: 5746876
    Abstract: A chemical apparatus is proposed where sampling of hazardous materials in semiconductor fabs, or manufacturing lines, is made easier and more productive. A sampler cup is provided which has a spout and a relatively long handle which in turn is equipped with a round shield fitted close to its end. The shield is used to protect the operator from the chemical effects and heat of the sampled substance. The cup is then placed into a second container, or a beaker, which has formed on its open edge notches where the long handle of the cup can be placed with ease. As a further means for secure placement, the cup has a recess at the bottom surface on the outside such that it captures a pedestal that is formed at the bottom of the beaker on the inside. Furthermore, the beaker has a handle which is protected by a still another protective sleeve formed in cylindrical shape around the handle. In this manner, the cup is held in one hand, while the beaker in the other, and the hazardous material is transported readily.
    Type: Grant
    Filed: June 3, 1996
    Date of Patent: May 5, 1998
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shun-Long Chen, Kuo-Yue Hsu
  • Patent number: 5701174
    Abstract: A method for optically inspecting a semiconductor substrate for defects such as oxidation induced stacking faults, and a template mask which assists in practicing the optical inspection method. There is first provided a semiconductor substrate which has a surface to be inspected for defects such as oxidation induced stacking faults. Aligned then upon the surface of the semiconductor substrate to be inspected for defects such as oxidation induced stacking faults is a template mask. The template mask has a minimum of one aperture which leaves exposed a portion of the surface of the semiconductor substrate to be inspected for defects such as oxidation induced stacking faults. Finally, there is inspected optically the portion of the surface of the semiconductor substrate exposed through the aperture.
    Type: Grant
    Filed: July 15, 1996
    Date of Patent: December 23, 1997
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Ching Hua Yeh, Shun-Long Chen