Patents by Inventor Shun-Min Yeh
Shun-Min Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230102875Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor structure is formed on a first surface of a silicon substrate. The semiconductor structure has a first surface facing the silicon substrate. At least one outer circuit is bonded to the semiconductor structure. A molding compound layer is formed covering a second surface of the silicon substrate. A part of the molding compound layer is removed for exposing the silicon substrate. The silicon substrate is removed for exposing the first surface of the semiconductor structure.Type: ApplicationFiled: October 13, 2021Publication date: March 30, 2023Applicant: GLC SEMI CONDUCTOR GROUP (SH) CO., LTD.Inventors: Chi-Ching Pu, Shun-Min Yeh
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Publication number: 20230053074Abstract: A semiconductor device includes at least one active region, a first dielectric layer, a gate structure, and an air void. The active region includes a III-V compound semiconductor layer. The first dielectric layer is disposed on the active region. The gate structure is disposed on the active region, and at least a part of the gate structure is disposed in the first dielectric layer. The air void is disposed in the first dielectric layer, and at least a part of the air void is disposed at two opposite sides of the gate structure in a horizontal direction.Type: ApplicationFiled: August 12, 2021Publication date: February 16, 2023Applicant: GLC SEMI CONDUCTOR GROUP (SH) CO., LTD.Inventors: Che-Jui Chang, Chi-Ching Pu, Shun-Min Yeh
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Publication number: 20220286125Abstract: A power switch circuit includes an internal node; a first field-effect transistor including a first drain, a first gate and a first source; a second field-effect transistor including a second drain, a second gate and a second source, wherein the first drain is coupled to a voltage supply terminal, the first gate is coupled to the second source, the first source and the second drain are coupled to the internal node, and the second source is coupled to a ground; and a regulating circuit is coupled to the internal node, wherein the regulating circuit is configured to regulate a voltage value of the internal node after the power switch circuit is activated.Type: ApplicationFiled: December 7, 2021Publication date: September 8, 2022Applicant: GLC SEMI CONDUCTOR GROUP (SH) CO., LTD.Inventors: Kuo-Chang Kao, Chi-Ching Pu, Shun-Min Yeh
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Patent number: 11411099Abstract: A semiconductor device includes a substrate, a first III-V compound layer, a gate electrode, drain trenches, and at least one drain electrode. The drain trenches are disposed and arranged with high integrity. The substrate has a first side and a second side opposite to the first side. The first III-V compound layer is disposed at the first side of the substrate. The gate electrode is disposed on the first III-V compound layer. Each of the drain trenches extends from the second side of the substrate toward the first side of the substrate and penetrates the substrate. The drain trenches are arranged regularly. The drain electrode is disposed in at least one of the drain trenches.Type: GrantFiled: July 23, 2019Date of Patent: August 9, 2022Assignee: GLC SEMICONDUCTOR GROUP (CQ) CO., LTD.Inventors: Chi-Ching Pu, Shun-Min Yeh
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Patent number: 10872967Abstract: A manufacturing method of a semiconductor device includes the following steps. At least one mesa structure is provided. The mesa structure includes a III-V compound semiconductor layer. A passivation layer is formed on the mesa structure. A gate dielectric layer is formed on the passivation layer, and a gate electrode is formed on the gate dielectric layer. An etching process is performed to the gate dielectric layer for thinning the gate dielectric layer before the step of forming the gate electrode. The thickness of the gate dielectric layer may be modified by the etching process, and the electrical performance of the semiconductor device may be enhanced accordingly.Type: GrantFiled: July 24, 2019Date of Patent: December 22, 2020Assignee: GLC SEMICONDUCTOR GROUP (CQ) CO., LTD.Inventors: Yi-Chun Shih, Shun-Min Yeh
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Publication number: 20200381554Abstract: A semiconductor device includes a substrate, a first III-V compound layer, a gate electrode, drain trenches, and at least one drain electrode. The drain trenches are disposed and arranged with high integrity. The substrate has a first side and a second side opposite to the first side. The first III-V compound layer is disposed at the first side of the substrate. The gate electrode is disposed on the first III-V compound layer. Each of the drain trenches extends from the second side of the substrate toward the first side of the substrate and penetrates the substrate. The drain trenches are arranged regularly. The drain electrode is disposed in at least one of the drain trenches.Type: ApplicationFiled: July 23, 2019Publication date: December 3, 2020Inventors: Chi-Ching Pu, Shun-Min Yeh
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Publication number: 20200381538Abstract: A manufacturing method of a semiconductor device includes the following steps. A substrate is provided. The substrate has a first side and a second side opposite to the first side. A first III-V compound layer is formed at the first side of the substrate. A drain trench and a contact trench are formed at the second side of the substrate. The drain trench extends from the second side of the substrate toward the first side of the substrate and penetrates the substrate. The contact trench extends from the second side of the substrate toward the first side of the substrate and penetrates the substrate. The drain trench and the contact trench are formed concurrently by the same process. A drain electrode is formed in the drain trench. A back contact structure is formed in the contact trench.Type: ApplicationFiled: July 24, 2019Publication date: December 3, 2020Inventors: Yi-Chun Shih, Shun-Min Yeh
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Patent number: 10854734Abstract: A manufacturing method of a semiconductor device includes the following steps. A substrate is provided. The substrate has a first side and a second side opposite to the first side. A first III-V compound layer is formed at the first side of the substrate. A drain trench and a contact trench are formed at the second side of the substrate. The drain trench extends from the second side of the substrate toward the first side of the substrate and penetrates the substrate. The contact trench extends from the second side of the substrate toward the first side of the substrate and penetrates the substrate. The drain trench and the contact trench are formed concurrently by the same process. A drain electrode is formed in the drain trench. A back contact structure is formed in the contact trench.Type: GrantFiled: July 24, 2019Date of Patent: December 1, 2020Assignee: GLC SEMICONDUCTOR GROUP (CQ) CO., LTD.Inventors: Yi-Chun Shih, Shun-Min Yeh
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Publication number: 20200373407Abstract: A manufacturing method of a semiconductor device includes the following steps. At least one mesa structure is provided. The mesa structure includes a III-V compound semiconductor layer. A passivation layer is formed on the mesa structure. A gate dielectric layer is formed on the passivation layer, and a gate electrode is formed on the gate dielectric layer. An etching process is performed to the gate dielectric layer for thinning the gate dielectric layer before the step of forming the gate electrode. The thickness of the gate dielectric layer may be modified by the etching process, and the electrical performance of the semiconductor device may be enhanced accordingly.Type: ApplicationFiled: July 24, 2019Publication date: November 26, 2020Inventors: Yi-Chun Shih, Shun-Min Yeh
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Patent number: 6645869Abstract: An etching back process to improve topographic planarization of a polysilicon layer. First, a polysilicon layer is formed to fill a contact hole between two adjacent insulating structures and cover the entire surface of a semiconductor substrate to a predetermined height, in which a sunken portion is formed in the polysilicon layer over the contact hole. Then, a bottom antireflective coating (BARC) layer is formed to fill the sunken portion and cover the entire surface of the polysilicon layer. Next, in a first etching step, the BARC layer outside the sunken portion of the polysilicon layer is removed and the BARC layer in the sunken portion of the polysilicon layer is retained to flatten the bottom of the sunken portion.Type: GrantFiled: September 26, 2002Date of Patent: November 11, 2003Assignee: Vanguard International Semiconductor CorporationInventors: Ching-Yun Chu, Chyei-Jer Hsieh, Teng-Shao Su, Shun-Min Yeh