Patents by Inventor SHUN YAMAGUCHI
SHUN YAMAGUCHI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11895770Abstract: A copper-clad laminate includes an insulating layer and a copper foil in contact with at least one surface of the insulating layer, in which the insulating layer contains a cured product of a resin composition containing a modified polyphenylene ether compound of which a terminal is modified with a substituent having a carbon-carbon unsaturated double bond, a chromium element amount on an exposed surface on which the insulating layer is exposed by an etching treatment of the copper-clad laminate with a copper chloride solution, measured by X-ray photoelectron spectroscopy is 7.5 at % or less with respect to a total element amount measured by X-ray photoelectron spectroscopy, and a surface roughness of the exposed surface is 2.0 ?m or less in terms of ten-point average roughness.Type: GrantFiled: September 27, 2019Date of Patent: February 6, 2024Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Yuki Inoue, Tatsuya Arisawa, Shun Yamaguchi
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Publication number: 20240001843Abstract: To provide a display device enabled to convey information appropriately. A display device according to the present embodiment includes a display that displays, in a display area, a warning indicator for notifying a viewer of a warning object located outside a vehicle and an attention-grabbing indicator for drawing attention of the viewer to the warning indicator; and a display controller that controls and directs, upon detection of the warning object, the display to display the warning indicator in the display area at a warning position corresponding to the warning object and to display the attention-grabbing indicator in such a manner that the attention-grabbing indicator advances from a position other than the warning position toward the warning position.Type: ApplicationFiled: June 26, 2023Publication date: January 4, 2024Inventor: Shun Yamaguchi
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Publication number: 20230347017Abstract: A sheet-shaped cell culture for covering a cut surface of a pancreas, the cut surface of the pancreas includes cut surfaces of a pancreatic parenchyma and a pancreatic duct, and is connected to an intestinal wall of a small intestine in a liquid-tight manner via the sheet-shaped cell culture. A method for preventing or treating pancreatic fistula includes a step of covering, using a sheet-shaped cell culture, a cut surface of a pancreas that includes cut surfaces of a pancreatic parenchyma and a pancreatic duct, and a step of connecting the cut surface of the pancreas to an intestinal wall of a small intestine in a liquid-tight manner via the sheet-shaped cell culture.Type: ApplicationFiled: June 29, 2023Publication date: November 2, 2023Inventors: Yasuhiro MARUYA, Shun YAMAGUCHI, Kengo KANETAKA, Susumu EGUCHI, Miki HIGASHI, Fumiya OHASHI, Miho KAI, Naoki ARAMAKI
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Publication number: 20230094806Abstract: A metal-clad laminate includes an insulating layer that contains a cured product of a resin composition containing a polymer having a structural unit represented by Formula (1) in a molecule and a metal foil that is laminated on the insulating layer and is a metal foil in which a nickel element amount on a surface on a side in contact with the insulating layer and a nickel element amount on the surface when the surface is sputtered for 1 minute at 3 nm/min in terms of SiO2 are each 4.5 at % or less with respect to the total element amount on each surface. In Formula (1), Z represents an arylene group, R1-R3 each independently represent a hydrogen atom or an alkyl group, and R4-R6 each independently represent a hydrogen atom or an alkyl group having 1-6 carbon atoms.Type: ApplicationFiled: October 15, 2020Publication date: March 30, 2023Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Akira IRIFUNE, Shun YAMAGUCHI, Fuminori SATOU, Tatsuya ARISAWA, Mitsuyoshi NISHINO
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Publication number: 20220347345Abstract: A bioadhesive sheet-shaped material configured to be attached onto a surface of an organ, a method for producing the bioadhesive sheet-shaped material, and a method for treating a disease by using the bioadhesive sheet-shaped material. The bioadhesive sheet-shaped material includes an extracellular matrix layer, a sheet-shaped cell culture, and a biodegradable gel layer, where the sheet-shaped cell culture is interposed between the extracellular matrix layer and the biodegradable gel layer, and the bioadhesive sheet-shaped material is by attaching the extracellular matrix layer onto a surface of an organ.Type: ApplicationFiled: July 20, 2022Publication date: November 3, 2022Applicants: NAGASAKI UNIVERSITY, TERUMO KABUSHIKI KAISHAInventors: Yasuhiro MARUYA, Shun YAMAGUCHI, Kengo KANETAKA, Miki HIGASHI, Susumu EGUCHI, Fumiya OHASHI, Masaki MATSUMURA
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Publication number: 20220015230Abstract: A copper-clad laminate includes an insulating layer and a copper foil in contact with at least one surface of the insulating layer, in which the insulating layer contains a cured product of a resin composition containing a modified polyphenylene ether compound of which a terminal is modified with a substituent having a carbon-carbon unsaturated double bond, a chromium element amount on an exposed surface on which the insulating layer is exposed by an etching treatment of the copper-clad laminate with a copper chloride solution, measured by X-ray photoelectron spectroscopy is 7.5 at % or less with respect to a total element amount measured by X-ray photoelectron spectroscopy, and a surface roughness of the exposed surface is 2.0 ?m or less in terms of ten-point average roughness.Type: ApplicationFiled: September 27, 2019Publication date: January 13, 2022Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Yuki INOUE, Tatsuya ARISAWA, Shun YAMAGUCHI
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Publication number: 20210395452Abstract: A metal-clad laminate includes an insulating layer, and a metal foil in contact with at least one surface of the insulating layer, in which the insulating layer contains a cured product of a resin composition containing a polyphenylene ether compound, and the metal foil is a metal foil in which a first nickel element amount, on a surface on a side in contact with the insulating layer, measured by X-ray photoelectron spectroscopy is 4.5 at % or less with respect to a total element amount measured by X-ray photoelectron spectroscopy, and a second nickel element amount, on a surface on a side in contact with the insulating layer when the surface is sputtered for 1 minute at a speed of 3 nm/min in terms of SiO2, measured by X-ray photoelectron spectroscopy is 4.5 at % or less with respect to a total element amount measured by X-ray photoelectron spectroscopy.Type: ApplicationFiled: September 27, 2019Publication date: December 23, 2021Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Tatsuya ARISAWA, Shun YAMAGUCHI, Fuminori SATOU, Akira IRIFUNE, Mitsuyoshi NISHINO
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Patent number: 9293564Abstract: A method of manufacturing a semiconductor device includes forming a first parallel pn layer; depositing a first-conductivity-type first semiconductor layer on a surface of the first parallel pn layer in a step that further includes forming a second parallel pn layer by selectively introducing second-conductivity-type impurities into the first semiconductor layer; and forming first second-conductivity-type impurity regions in positions opposed in a depth direction to regions of the first parallel pn layer in which second-conductivity-type semiconductor regions are formed; and forming a local insulating film on a surface of the first semiconductor layer in a termination structure portion so that an end portion of the local insulating film is positioned on the first second-conductivity-type impurity region, by heating at a low temperature effective to suppress diffusion of the first second-conductivity-type impurity regions.Type: GrantFiled: May 12, 2015Date of Patent: March 22, 2016Assignee: FUJI ELECTRIC CO., LTD.Inventors: Takeyoshi Nishimura, Shun Yamaguchi, Toshiaki Sakata
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Publication number: 20150364577Abstract: A method of manufacturing a semiconductor device includes forming a first parallel pn layer; depositing a first-conductivity-type first semiconductor layer on a surface of the first parallel pn layer in a step that further includes forming a second parallel pn layer by selectively introducing second-conductivity-type impurities into the first semiconductor layer; and forming first second-conductivity-type impurity regions in positions opposed in a depth direction to regions of the first parallel pn layer in which second-conductivity-type semiconductor regions are formed; and forming a local insulating film on a surface of the first semiconductor layer in a termination structure portion so that an end portion of the local insulating film is positioned on the first second-conductivity-type impurity region, by heating at a low temperature effective to suppress diffusion of the first second-conductivity-type impurity regions.Type: ApplicationFiled: May 12, 2015Publication date: December 17, 2015Applicant: FUJI ELECTRIC CO., LTD.Inventors: Takeyoshi NISHIMURA, Shun YAMAGUCHI, Toshiaki SAKATA
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Patent number: 9152012Abstract: A power source switching device includes a first switch circuit provided between a first power source and a load section, a second switch circuit provided between a second power source and the load section, a third switch circuit provided between the first power source and the load section in series with the first switch circuit, a fourth switch circuit provided between the second power source and the load section in series with the second switch circuit, a logic circuit that controls the third and the fourth switch circuits to prevent at least one of the third and fourth switch circuits from turning on while both of the first and second switch circuits are in an on state, and a control circuit that controls the first switch circuit, the second switch circuit, and the logic circuit.Type: GrantFiled: April 16, 2013Date of Patent: October 6, 2015Assignee: Panosonic Intellectual Property Management Co., Ltd.Inventor: Shun Yamaguchi
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Patent number: 9086612Abstract: There is provided an interchangeable lens mountable to a camera body. The interchangeable lens includes a zoom lens which can change a field angle of a subject image, a receiving unit for receiving sound pickup property information from the camera body, the sound pickup property information indicating sound pickup property of the camera body, and a lens controller for controlling drive of the zoom lens. The lens controller decides an available driving speed based on the sound collecting property information, the available driving speed being a driving speed settable to the zoom lens.Type: GrantFiled: October 3, 2012Date of Patent: July 21, 2015Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Jin Korekuni, Yoshio Ohtsuka, Yasuhiro Wada, Yasunori Nakai, Shun Yamaguchi
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Publication number: 20130272691Abstract: A power source switching device includes a first switch circuit provided between a first power source and a load section, a second switch circuit provided between a second power source and the load section, a third switch circuit provided between the first power source and the load section in series with the first switch circuit, a fourth switch circuit provided between the second power source and the load section in series with the second switch circuit, a logic circuit that controls the third and the fourth switch circuits to prevent at least one of the third and fourth switch circuits from turning on while both of the first and second switch circuits are in an on state, and a control circuit that controls the first switch circuit, the second switch circuit, and the logic circuit.Type: ApplicationFiled: April 16, 2013Publication date: October 17, 2013Applicant: PANASONIC CORPORATIONInventor: SHUN YAMAGUCHI