Abstract: An oversampling data recovery circuit for a receiver comprises a plurality of sampling circuits for sampling an input data upon a plurality of clocks to generate a plurality of sample data, respectively, an edge detector for determining an edge of the input data by monitoring the plurality of sample data, and a state machine for selecting one from the plurality of sample data as an output data of the oversampling data recovery circuit according to the edge of the input data, such that the receiver will have an optimum timing margin.

Abstract: An oversampling data recovery circuit for a receiver comprises a plurality of sampling circuits for sampling an input data upon a plurality of clocks to generate a plurality of sample data, respectively, an edge detector for determining an edge of the input data by monitoring the plurality of sample data, and a state machine for selecting one from the plurality of sample data as an output data of the oversampling data recovery circuit according to the edge of the input data, such that the receiver will have an optimum timing margin.

Abstract: The present invention provides a termination circuit with voltage-independent characteristics. The termination impedance circuit provided is coupled to a transmission line from a driver circuit. The termination impedance circuit includes a transistor-type resistor of a size A, and an impedance compensation circuit. The transistor-type resistor of a size A is operative to receive a first control signal and has a node coupled to the transmission line. The impedance compensation circuit includes a pair of transistors and a transistor of size B. The ratio of (A/B) is such that a substantial constant output impedance is achieved as large pull-down or pull-up voltage excursion at the transmission line occurs.

Abstract: The present invention discloses an output driver circuit providing linear I/V characteristics, i.e. constant output impedance, during output voltage transitions. The output driver circuit includes a first input transistor, a second input transistor, a first pair of transistors, a second pair of transistors, a first output transistor and a second output transistor. The first input transistor inputs a first input signal and has an output node coupled to the output node of the output driver circuit. The second input transistor inputs a second input signal and has an output node coupled to the output node of the output driver circuit. The first pair of transistors is responsive to a first control signal and the output signal for generating a second control signal. The second pair of transistors is responsive to a third control signal and the output signal for generating a fourth control signal.