Abstract: The present disclosure relates to software-defined methods and apparatuses for designing a wafer-level switching system, including: determining wafer-level switching system layout constraints; constructing a target wafer-level switching system and determining parameters, and designing a logical topology of a switching network; designing a layout of the switching chiplets on the wafer substrate; respectively designing interface structures of external chiplets and internal chiplets; configuring a switching mode and an enable state of each port of the switching chiplets; ending the process when the target logical topology can be achieved by the wafer-level switching system; otherwise, reconstructing a logical topology of a switching network and mapping it to the substrate.

Abstract: A method comprises obtaining a test specification document of a user, wherein the test specification document comprises a test scheme based on a natural language; recommending, to the user and based on a first test step in the test scheme, a test interface set comprising a plurality of test interfaces for implementing a second test step, performing, by the user, a selection operation on the test interfaces in the test interface set; and generating, based on the selection operation, one or more test cases.

Abstract: A wafer-level heterogeneous dies integration structure and method are provided. The integration structure includes a wafer substrate, a silicon interposer, heterogeneous dies, and a configuration substrate. A standard integration module is defined by the heterogeneous dies connected to the silicon interposer. The standard integration module is connected to an upper surface of the wafer substrate, and the configuration substrate is connected to a lower surface of the wafer substrate. The wafer substrate is connected to the configuration substrate via Through Silicon Vias on lower surface of the wafer substrate. And the upper surface of the wafer substrate is provided with Re-distributed Layers and a standardized micro bump array to form standard integration zone connected to the standard integration module.

Abstract: The present disclosure relates to software-defined methods and apparatuses for designing a wafer-level switching system, including: determining wafer-level switching system layout constraints; constructing a target wafer-level switching system and determining parameters, and designing a logical topology of a switching network; designing a layout of the switching chiplets on the wafer substrate; respectively designing interface structures of external chiplets and internal chiplets; configuring a switching mode and an enable state of each port of the switching chiplets; ending the process when the target logical topology can be achieved by the wafer-level switching system; otherwise, reconstructing a logical topology of a switching network and mapping it to the substrate.

Abstract: A wafer-level heterogeneous dies integration structure and method are provided. The integration structure includes a wafer substrate, a silicon interposer, heterogeneous dies, and a configuration substrate. A standard integration module is defined by the heterogeneous dies connected to the silicon interposer. The standard integration module is connected to an upper surface of the wafer substrate, and the configuration substrate is connected to a lower surface of the wafer substrate. The wafer substrate is connected to the configuration substrate via Through Silicon Vias on lower surface of the wafer substrate. And the upper surface of the wafer substrate is provided with Re-distributed Layers and a standardized micro bump array to form standard integration zone connected to the standard integration module.

Abstract: A system-on-wafer structure and a fabrication method. The structure includes a wafer substrate, an integrated chiplet, a system configuration board and a thermal module. The wafer substrate and the integrated chiplet are bonded through a wafer micro bump array and a chiplet micro bump array. The wafer substrate and the system configuration board are bonded through a copper pillar array on wafer substrate topside and a pad on system configuration board backside. A molding layer is provided between the wafer substrate and the system configuration board, and is configured to mold the wafer substrate, the integrated chiplet and the copper pillar array. Integrated chiplet are electrically connected to each other through a re-distributed layer in wafer substrate. The integrated chiplet is electrically connected to the system configuration board through the re-distributed layer and the copper pillar array. The thermal module is attached to the backside of the wafer substrate.

Abstract: A routing structure and a method of a wafer substrate with standard integration zone for integration on-wafer, which comprises a core voltage network, an interconnection signal network, a clock signal network and a ground network, wherein the core voltage network and the interconnection signal network belong to a top metal layer, the clock signal network is located in a inner metal layer, and the ground network is located in a bottom metal layer. The pins provided on the standard zone include core voltage pins, interconnection signal pins, clock signal pins, ground pins, and complex function pins. The complex function pins are directly connected to the outside of the system by TSV at the bottom of the wafer, and the other pins are connected by their signal networks. The present disclosure solves the yield problem with few metal layers of the wafer substrate for SoW.

Abstract: A system-on-wafer structure and a fabrication method. The structure includes a wafer substrate, an integrated chiplet, a system configuration board and a thermal module. The wafer substrate and the integrated chiplet are bonded through a wafer micro bump array and a chiplet micro bump array. The wafer substrate and the system configuration board are bonded through a copper pillar array on wafer substrate topside and a pad on system configuration board backside. A molding layer is provided between the wafer substrate and the system configuration board, and is configured to mold the wafer substrate, the integrated chiplet and the copper pillar array. Integrated chiplet are electrically connected to each other through a re-distributed layer in wafer substrate. The integrated chiplet is electrically connected to the system configuration board through the re-distributed layer and the copper pillar array. The thermal module is attached to the backside of the wafer substrate.

Abstract: Disclosed are an input/output proxy method and apparatus for a mimic Redis database. Through a pseudo server module, it is ensured that the interface of the Redis database is consistent with the external interface of the native Redis, so that it is convenient to implant the Redis database into arbitrary Redis application scenarios; the isolation of the modules inside is realized by independent processes, thus facilitating independent development, maintenance and expansion; and the synchronization function is integrated into the input/output proxy to achieve resource reuse; for the synchronization function, the random credit attenuation mechanism is cleverly utilized to ensure the synchronization function while taking into account the saving of resources.

Abstract: Disclosed are an input/output proxy method and apparatus for a mimic Redis database. Through a pseudo server module, it is ensured that the interface of the Redis database is consistent with the external interface of the native Redis, so that it is convenient to implant the Redis database into arbitrary Redis application scenarios; the isolation of the modules inside is realized by independent processes, thus facilitating independent development, maintenance and expansion; and the synchronization function is integrated into the input/output proxy to achieve resource reuse; for the synchronization function, the random credit attenuation mechanism is cleverly utilized to ensure the synchronization function while taking into account the saving of resources.

Abstract: The present disclosure discloses a three-dimensional stacked package structure with a micro-channel heat dissipation structure and a packaging method thereof. The three-dimensional stacked package structure includes a chip package portion comprising a multi-layered structure with stacked chips, wherein the stacked chips are provided with through silicon vias and packaged in a three-dimensional stacked packaging manner and a silicon substrate package portion comprising a silicon substrate. The silicon substrate is provided with micro bumps which are to be interconnected with external lead wires. The chip package portion is assembled on the silicon substrate by bonding with the micro bumps. The stacked chips are etched with micro-channels and through holes corresponding to each other. The micro-channels are for coolant flowing in a horizontal direction, and the through holes are for coolant flowing in upper and lower layers. Sealing rings are arranged around the micro-channels and the through holes.

Abstract: An interconnection structure of a system on wafer and a PCB based on a TSV process and a method for manufacturing the same. The structure comprises a bottom structural part and a top structural part, the upper surface of the bottom structural part is provided with a plurality of positioning holes; the lower surface of the top structural part is provided with positioning pins; the upper surface of the bottom structural part is provided with a bottom groove, and a system on wafer is arranged in the bottom groove; the lower surface of the system on wafer is connected with the bottom groove; the lower surface of the top structural part is provided with a top groove, and a PCB preformed die is connected in the top groove, and the other end of the PCB preformed die is connected with the system on wafer by an elastic connector.

Abstract: The present disclosure belongs to an identity authentication technology in network security field, and relates to a lightweight identity authentication method. The method utilizes lightweight operations of the physical unclonable function, Hash operation, XOR operation, etc.

Abstract: An apparatus for remediation of a copper and nickel co-contaminated soil includes a housing. A crushing device is arranged at the upper part of the inside of the housing. A stirring device is arranged below the crushing device. An anode electrode and a cathode electrode are provided at both ends of the inner bottom of the housing, respectively. In the present invention, the soil contaminated by copper and nickel is first poured from the top of the crushing device, and then crushed thoroughly under the action of the crushing device. The crushed soil facilitates the movement of copper and nickel metal ions therein toward the electrodes under the action of the anode electrode and the cathode electrode, thereby achieving optimal soil remediation.

Abstract: An apparatus for remediation of a copper and nickel co-contaminated soil includes a housing. A crushing device is arranged at the upper part of the inside of the housing. A stirring device is arranged below the crushing device. An anode electrode and a cathode electrode are provided at both ends of the inner bottom of the housing, respectively. In the present invention, the soil contaminated by copper and nickel is first poured from the top of the crushing device, and then crushed thoroughly under the action of the crushing device. The crushed soil facilitates the movement of copper and nickel metal ions therein toward the electrodes under the action of the anode electrode and the cathode electrode, thereby achieving optimal soil remediation.

Abstract: Disclosed is a method for establishing an X2 interface IPSec tunnel. The method comprises: obtaining, by using SI signaling, IP information of a peer end base station for establishing an inter-base station X2 interface coupling link; automatically generating or receiving configuration data automatically generated and delivered by an operation and maintenance center and used for establishing the inter-base station X2 interface coupling link and configuration data used for establishing an inter-base station X2 interface IPSec tunnel; generating an X2 interface coupling packet according to the configuration data used for establishing the inter-base station X2 interface coupling link; and generating an IPSec negotiation packet according to the configuration data used for establishing the inter-base station X2 interface IPSec tunnel, and triggering the establishment of the inter-base station X2 interface IPSec tunnel by using the X2 interface coupling packet.

Abstract: Disclosed is a method for establishing an X2 interface IPSec tunnel. The method comprises: obtaining, by using S1 signaling, IP information of a peer end base station for establishing an inter-base station X2 interface coupling link; automatically generating or receiving configuration data automatically generated and delivered by an operation and maintenance center and used for establishing the inter-base station X2 interface coupling link and configuration data used for establishing an inter-base station X2 interface IPSec tunnel; generating an X2 interface coupling packet according to the configuration data used for establishing the inter-base station X2 interface coupling link; and generating an IPSec negotiation packet according to the configuration data used for establishing the inter-base station X2 interface IPSec tunnel, and triggering the establishment of the inter-base station X2 interface IPSec tunnel by using the X2 interface coupling packet.