Abstract: The present disclosure relates to software-defined methods and apparatuses for designing a wafer-level switching system, including: determining wafer-level switching system layout constraints; constructing a target wafer-level switching system and determining parameters, and designing a logical topology of a switching network; designing a layout of the switching chiplets on the wafer substrate; respectively designing interface structures of external chiplets and internal chiplets; configuring a switching mode and an enable state of each port of the switching chiplets; ending the process when the target logical topology can be achieved by the wafer-level switching system; otherwise, reconstructing a logical topology of a switching network and mapping it to the substrate.

Abstract: A method comprises obtaining a test specification document of a user, wherein the test specification document comprises a test scheme based on a natural language; recommending, to the user and based on a first test step in the test scheme, a test interface set comprising a plurality of test interfaces for implementing a second test step, performing, by the user, a selection operation on the test interfaces in the test interface set; and generating, based on the selection operation, one or more test cases.