Patents by Inventor Shunguang Ding

Shunguang Ding has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Robust and economic solution for FPGA bit file upgrade
    Patent number: 7772882
    Abstract: A system for FPGA (Field Programmable Gate Array) upgrade includes: an FPGA, a FLASH memory and a CPLD. The FLASH memory includes a first section configured to store a workable version of bit files for the FPGA and a second section configured to store a backup version of bit files for the FPGA. The CPLD is coupled to the FPGA and the FLASH memory. The CPLD is configured to download the bit files from the FLASH memory to the FPGA to provide the FPGA with functionality. As a result, the CPLD communicates with CPU to upgrade the bit files in the FLASH memory, and indicates to the CPU which version of bit files has been downloaded to the FPGA.
    Type: Grant
    Filed: June 23, 2008
    Date of Patent: August 10, 2010
    Assignee: O2Micro International Limited
    Inventors: Licai Fang, Lin Gan, Shunguang Ding, Jyshyang Chen
  • ROBUST AND ECONOMIC SOLUTION FOR FPGA BITFILE UPGRADE
    Publication number: 20080252335
    Abstract: A system for FPGA (Field Programmable Gate Array) upgrade includes: an FPGA, a FLASH memory and a CPLD. The FLASH memory includes a first section configured to store a workable version of bit files for the FPGA and a second section configured to store a backup version of bit files for the FPGA. The CPLD is coupled to the FPGA and the FLASH memory. The CPLD is configured to download the bit files from the FLASH memory to the FPGA to provide the FPGA with functionality. As a result: the CPLD communicates with CPU to upgrade the bit files in the FLASH memory, and indicates to the CPU which version of bit files has been downloaded to the FPGA.
    Type: Application
    Filed: June 23, 2008
    Publication date: October 16, 2008
    Applicant: O2Micro, Inc.
    Inventors: Licai Fang, Lin Gan, Shunguang Ding, Jyshyang Chen
  • Robust and economic solution for FPGA bitfile upgrade
    Patent number: 7391237
    Abstract: A system for FPGA (Field Programmable Gate Array) upgrade includes: an FPGA, a FLASH memory and a CPLD. The FLASH memory includes a first section configured to store a workable version of bit files for the FPGA and a second section configured to store a backup version of bit files for the FPGA. The CPLD is coupled to the FPGA and the FLASH memory. The CPLD is configured to download the bit files from the FLASH memory to the FPGA to provide the FPGA with functionality. As a result, the CPLD communicates with CPU to upgrade the bit files in the FLASH memory, and indicates to the CPU which version of bit files has been downloaded to the FPGA.
    Type: Grant
    Filed: August 18, 2005
    Date of Patent: June 24, 2008
    Assignee: O2 Micro International Limited
    Inventors: Licai Fang, Lin Gan, Shunguang Ding, Jyshyang Chen
  • Robust and economic solution for FPGA bitfile upgrade
    Publication number: 20060244484
    Abstract: A system for FPGA (Field Programmable Gate Array) upgrade includes: an FPGA, a FLASH memory and a CPLD. The FLASH memory includes a first section configured to store a workable version of bit files for the FPGA and a second section configured to store a backup version of bit files for the FPGA. The CPLD is coupled to the FPGA and the FLASH memory. The CPLD is configured to download the bit files from the FLASH memory to the FPGA to provide the FPGA with functionality. As a result, the CPLD communicates with CPU to upgrade the bit files in the FLASH memory, and indicates to the CPU which version of bit files has been downloaded to the FPGA.
    Type: Application
    Filed: August 18, 2005
    Publication date: November 2, 2006
    Inventors: Licai Fang, Lin Gan, Shunguang Ding, Jyshyang Chen