Patents by Inventor Shunhua Chang
Shunhua Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10359461Abstract: A method of protecting devices within an integrated circuit during electro-static discharge (ESD) testing using an ESD test system is provided. The method includes applying a direct current (DC) bias voltage to an input of at least one device of the integrated circuit and applying an ESD simulated signal to at least one other input of the integrated circuit. The applied ESD simulated signal is conducted along a first current path to a first ground, while a low-current signal associated with the at least one device is conducted along a second current path to the second ground. The DC bias voltage is maintained between the input of the at least one device and the second ground at a substantially constant value in response to a signal variation on the second ground that results from the applied ESD simulated signal.Type: GrantFiled: December 7, 2017Date of Patent: July 23, 2019Assignee: International Business Machines CorporationInventors: Shunhua Chang, James Paul Di Sarro, Robert J. Gauthier, Jr., Nathan Jack, Souvick Mitra
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Publication number: 20180100883Abstract: A method of protecting devices within an integrated circuit during electro-static discharge (ESD) testing using an ESD test system is provided. The method includes applying a direct current (DC) bias voltage to an input of at least one device of the integrated circuit and applying an ESD simulated signal to at least one other input of the integrated circuit. The applied ESD simulated signal is conducted along a first current path to a first ground, while a low-current signal associated with the at least one device is conducted along a second current path to the second ground. The DC bias voltage is maintained between the input of the at least one device and the second ground at a substantially constant value in response to a signal variation on the second ground that results from the applied ESD simulated signal.Type: ApplicationFiled: December 7, 2017Publication date: April 12, 2018Inventors: SHUNHUA CHANG, JAMES PAUL DI SARRO, ROBERT J. GAUTHIER, JR., NATHAN JACK, SOUVICK MITRA
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Publication number: 20180100884Abstract: A method of protecting devices within an integrated circuit during electro-static discharge (ESD) testing using an ESD test system is provided. The method includes applying a direct current (DC) bias voltage to an input of at least one device of the integrated circuit and applying an ESD simulated signal to at least one other input of the integrated circuit. The applied ESD simulated signal is conducted along a first current path to a first ground, while a low-current signal associated with the at least one device is conducted along a second current path to the second ground. The DC bias voltage is maintained between the input of the at least one device and the second ground at a substantially constant value in response to a signal variation on the second ground that results from the applied ESD simulated signal.Type: ApplicationFiled: December 7, 2017Publication date: April 12, 2018Inventors: SHUNHUA CHANG, JAMES PAUL DI SARRO, ROBERT J. GAUTHIER, JR., NATHAN JACK, SOUVICK MITRA
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Patent number: 9869708Abstract: A method of protecting devices within an integrated circuit during electro-static discharge (ESD) testing using an ESD test system is provided. The method includes applying a direct current (DC) bias voltage to an input of at least one device of the integrated circuit and applying an ESD simulated signal to at least one other input of the integrated circuit. The applied ESD simulated signal is conducted along a first current path to a first ground, while a low-current signal associated with the at least one device is conducted along a second current path to the second ground. The DC bias voltage is maintained between the input of the at least one device and the second ground at a substantially constant value in response to a signal variation on the second ground that results from the applied ESD simulated signal.Type: GrantFiled: October 14, 2015Date of Patent: January 16, 2018Assignee: International Business Machines CorporationInventors: Shunhua Chang, James Paul Di Sarro, Robert J. Gauthier, Jr., Nathan Jack, Souvick Mitra
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Patent number: 9435841Abstract: A method of protecting devices within an integrated circuit during electro-static discharge (ESD) testing using an ESD test system is provided. The method includes applying a direct current (DC) bias voltage to an input of at least one device of the integrated circuit and applying an ESD simulated signal to at least one other input of the integrated circuit. The applied ESD simulated signal is conducted along a first current path to a first ground, while a low-current signal associated with the at least one device is conducted along a second current path to the second ground. The DC bias voltage is maintained between the input of the at least one device and the second ground at a substantially constant value in response to a signal variation on the second ground that results from the applied ESD simulated signal.Type: GrantFiled: April 13, 2012Date of Patent: September 6, 2016Assignee: International Business Machines CorporationInventors: Shunhua Chang, James Paul Di Sarro, Robert J. Gauthier, Jr., Nathan Jack, Souvick Mitra
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Publication number: 20160033564Abstract: A method of protecting devices within an integrated circuit during electro-static discharge (ESD) testing using an ESD test system is provided. The method includes applying a direct current (DC) bias voltage to an input of at least one device of the integrated circuit and applying an ESD simulated signal to at least one other input of the integrated circuit. The applied ESD simulated signal is conducted along a first current path to a first ground, while a low-current signal associated with the at least one device is conducted along a second current path to the second ground. The DC bias voltage is maintained between the input of the at least one device and the second ground at a substantially constant value in response to a signal variation on the second ground that results from the applied ESD simulated signal.Type: ApplicationFiled: October 14, 2015Publication date: February 4, 2016Inventors: SHUNHUA CHANG, JAMES PAUL DI SARRO, ROBERT J. GAUTHIER, JR., NATHAN JACK, SOUVICK MITRA
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Patent number: 8803276Abstract: A structure and method of fabricating electrostatic discharge (EDS) circuitry in an integrated circuit chip by integrating a lateral bipolar, either a p-n-p with a NMOSFET or a n-p-n with a PMOSFET within a triple well. The lateral bipolar preferably includes diodes at the I/O and/or the VDDs of the circuitry.Type: GrantFiled: November 6, 2013Date of Patent: August 12, 2014Assignee: International Business Machines CorporationInventors: Shunhua Chang, Kiran V. Chatty, Robert J. Gauthier, Mujahid Muhammad
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Publication number: 20140061803Abstract: A structure and method of fabricating electrostatic discharge (EDS) circuitry in an integrated circuit chip by integrating a lateral bipolar, either a p-n-p with a NMOSFET or a n-p-n with a PMOSFET within a triple well. The lateral bipolar preferably includes diodes at the I/O and/or the VDDs of the circuitry.Type: ApplicationFiled: November 6, 2013Publication date: March 6, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Shunhua CHANG, Kiran V. CHATTY, Robert J. GAUTHIER, JR., Mujahid MUHAMMAD
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Patent number: 8597993Abstract: A structure and method of fabricating electrostatic discharge (EDS) circuitry in an integrated circuit chip by integrating a lateral bipolar, either a p-n-p with a NMOSFET or a n-p-n with a PMOSFET within a triple well. The lateral bipolar preferably includes diodes at the I/O and/or the VDDs of the circuitry.Type: GrantFiled: March 14, 2008Date of Patent: December 3, 2013Assignee: International Business Machines CorporationInventors: Shunhua Chang, Kiran V. Chatty, Robert J. Gauthier, Jr., Mujahid Muhammad
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Publication number: 20130271883Abstract: A method of protecting devices within an integrated circuit during electro-static discharge (ESD) testing using an ESD test system is provided. The method includes applying a direct current (DC) bias voltage to an input of at least one device of the integrated circuit and applying an ESD simulated signal to at least one other input of the integrated circuit. The applied ESD simulated signal is conducted along a first current path to a first ground, while a low-current signal associated with the at least one device is conducted along a second current path to the second ground. The DC bias voltage is maintained between the input of the at least one device and the second ground at a substantially constant value in response to a signal variation on the second ground that results from the applied ESD simulated signal.Type: ApplicationFiled: April 13, 2012Publication date: October 17, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Shunhua Chang, James Paul Di Sarro, Robert J. Gauthier, JR., Nathan Jack, Souvick Mitra
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Patent number: 8354722Abstract: An electrostatic discharge (ESD) protection circuit, methods of fabricating an ESD protection circuit, methods of providing ESD protection, and design structures for an ESD protection circuit. An NFET may be formed in a p-well and a PFET may be formed in an n-well. A butted p-n junction formed between the p-well and n-well results in an NPNP structure that forms an SCR integrated with the NFET and PFET. The NFET, PFET and SCR are configured to collectively protect a pad, such as a power pad, from ESD events. During normal operation, the NFET, PFET, and SCR are biased by an RC-trigger circuit so that the ESD protection circuit is in a high impedance state. During an ESD event while the chip is unpowered, the RC-trigger circuit outputs trigger signals that cause the SCR, NFET, and PFET to enter into conductive states and cooperatively to shunt ESD currents away from the protected pad.Type: GrantFiled: May 31, 2011Date of Patent: January 15, 2013Assignee: International Business Machines CorporationInventors: John B. Campi, Jr., Shunhua Chang, Kiran V. Chatty, Robert J. Gauthier, Jr., Junjun Li, Rahul Mishra, Mujahid Muhammad
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Patent number: 8299533Abstract: A vertical NPNP structure fabricated using a triple well CMOS process, as well as methods of making the vertical NPNP structure, methods of providing electrostatic discharge (ESD) protection, and design structures for a BiCMOS integrated circuit. The vertical NPNP structure may be used to provide on-chip protection to an input/output (I/O) pad from negative-voltage ESD events. A vertical PNPN structure may be also used to protect the same I/O pad from positive-voltage ESD events.Type: GrantFiled: November 24, 2010Date of Patent: October 30, 2012Assignee: International Business Machines CorporationInventors: John B. Campi, Jr., Shunhua Chang, Kiran V. Chatty, Robert J. Gauthier, Jr., Junjun Li, Rahul Mishra, Mujahid Muhammad
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Publication number: 20090231766Abstract: A structure and method of fabricating electrostatic discharge (EDS) circuitry in an integrated circuit chip by integrating a lateral bipolar, either a p-n-p with a NMOSFET or a n-p-n with a PMOSFET within a triple well. The lateral bipolar preferably includes diodes at the I/O and/or the VDDs of the circuitry.Type: ApplicationFiled: March 14, 2008Publication date: September 17, 2009Inventors: Shunhua Chang, Kiran V. Chatty, Robert J. Gauthier, JR., Mujahid Muhammad
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Publication number: 20080116529Abstract: A semiconductor structure comprising a first field effect transistor (FET), a second FET, and a shallow trench isolation (STI) structure. The first FET comprises a channel region formed from a portion of a silicon substrate, a gate dielectric formed over the channel region, and a gate electrode comprising a bottom surface in direct physical contact with the gate dielectric. A top surface of the channel region is located within a first plane and the bottom surface of the gate electrode is located within a second plane. The STI structure comprises a conductive STI fill structure. A top surface of the conductive STI fill structure is above the first plane by a first distance D1 and is above the second plane by a second distance D2 that is less than D1.Type: ApplicationFiled: January 30, 2008Publication date: May 22, 2008Inventors: Ethan Cannon, Shunhua Chang, Toshiharu Furukawa, David Horak, Charles Koburger
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Publication number: 20070187778Abstract: A semiconductor structure and associated method for forming the semiconductor structure. The semiconductor structure comprises a first field effect transistor (FET), a second FET, and a shallow trench isolation (STI) structure. The first FET comprises a channel region formed from a portion of a silicon substrate, a gate dielectric formed over the channel region, and a gate electrode comprising a bottom surface in direct physical contact with the gate dielectric. A top surface of the channel region is located within a first plane and the bottom surface of the gate electrode is located within a second plane. The STI structure comprises a conductive STI fill structure. A top surface of the conductive STI fill structure is above the first plane by a first distance D1 and is above the second plane by a second distance D2 that is less than D1.Type: ApplicationFiled: February 15, 2006Publication date: August 16, 2007Inventors: Ethan Cannon, Shunhua Chang, Toshiharu Furukawa, David Horak, Charles Koburger
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Publication number: 20070158755Abstract: Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The structure comprises a first doped well formed in a substrate of semiconductor material, a second doped well formed in the substrate proximate to the first doped well, and a deep trench defined in the substrate. The deep trench includes sidewalls positioned between the first and second doped wells. A buried conductive region is defined in the semiconductor material bordering the base and the sidewalls of the deep trench. The buried conductive region intersects the first and second doped wells. The buried conductive region has a higher dopant concentration than the first and second doped wells. The buried conductive region may be formed by solid phase diffusion from a mobile dopant-containing material placed in the deep trench. After the buried conductive region is formed, the mobile dopant-containing material may optionally remain in the deep trench.Type: ApplicationFiled: January 12, 2006Publication date: July 12, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Shunhua Chang, Toshiharu Furukawa, Robert Gauthier, David Horak, Charles Koburger, Jack Mandelman, William Tonti