Abstract: The disclosure provides an apparatus for preventing an integrated circuit (IC) structure from entering a latch-up mode. In an embodiment, the apparatus may include: a p-type substrate; an n-well within the p-type substrate; an n-type region within the p-type substrate, the n-type region being distinct from the n-well; a p-type region within the n-well; a power supply electrically coupled to the p-type region within the n-well; and a directional diode electrically coupling the power supply to the n-well in parallel with the p-type region. The directional diode biases a current flow from the power supply to the n-well, and the directional diode contacts the n-well distal to the p-type region.

Abstract: The disclosure provides an apparatus for preventing an integrated circuit (IC) structure from entering a latch-up mode. In an embodiment, the apparatus may include: a p-type substrate; an n-well within the p-type substrate; an n-type region within the p-type substrate, the n-type region being distinct from the n-well; a p-type region within the n-well; a power supply electrically coupled to the p-type region within the n-well; and a directional diode electrically coupling the power supply to the n-well in parallel with the p-type region. The directional diode biases a current flow from the power supply to the n-well, and the directional diode contacts the n-well distal to the p-type region.

Abstract: An approach for transmission line pulse and very fast transmission line pulse reflection control is provided. The approach includes using a power splitter to split an incident pulse into two identical pulses with one going to a device under test (DUT) through a delivery cable and the other going down an open ended delay cable. The structure of the power splitter, along with having the delivery cable and the open ended delay cable with the same signal propagation time and pulse transmission characteristics enable the canceling of pulse reflections from the DUT.

Abstract: An approach for cancelling reverse reflections in very-fast transmission line pulse (VFTLP) testing of an electrostatic discharge (ESD) device in a semiconductor is provided. A method includes generating an incident pulse in a VFTLP system for applying to a device under test (DUT). The method also includes generating a delayed replica of the incident pulse. The method also includes cancelling a portion of a reverse reflection of the incident pulse by combining the delayed replica with the reverse reflection at a power divider.

Abstract: An approach for transmission line pulse and very fast transmission line pulse reflection control is provided. The approach includes using a power splitter to split an incident pulse into two identical pulses with one going to a device under test (DUT) through a delivery cable and the other going down an open ended delay cable. The structure of the power splitter, along with having the delivery cable and the open ended delay cable with the same signal propagation time and pulse transmission characteristics enable the canceling of pulse reflections from the DUT.

Abstract: An approach for cancelling reverse reflections in very-fast transmission line pulse (VFTLP) testing of an electrostatic discharge (ESD) device in a semiconductor is provided. A method includes generating an incident pulse in a VFTLP system for applying to a device under test (DUT). The method also includes generating a delayed replica of the incident pulse. The method also includes cancelling a portion of a reverse reflection of the incident pulse by combining the delayed replica with the reverse reflection at a power divider.

Abstract: An approach for cancelling reverse reflections in very-fast transmission line pulse (VFTLP) testing of an electrostatic discharge (ESD) device in a semiconductor is provided. A method includes generating an incident pulse in a VFTLP system for applying to a device under test (DUT). The method also includes generating a delayed replica of the incident pulse. The method also includes cancelling a portion of a reverse reflection of the incident pulse by combining the delayed replica with the reverse reflection at a power divider.

Abstract: A low leakage, low capacitance diode based triggered electrostatic discharge (ESD) silicon controlled rectifiers (SCR), methods of manufacture and design structure are provided. The method includes providing a silicon film on an insulator layer. The method further includes forming isolation regions which extend from an upper side of the silicon layer to the insulator layer. The method further includes forming one or more diodes in the silicon layer, including a p+ region and an n+ region formed in a well bordered by the isolation regions. The isolation regions isolate the one or more diodes in a vertical direction and the insulator layer isolates the one or more diodes from an underlying P or N type substrate, in a horizontal direction.

Abstract: A robust ESD protection circuit, method and design structure for tolerant and failsafe designs are disclosed. A circuit includes a middle junction control circuit that turns off a top NFET of a stacked NFET electrostatic discharge (ESD) protection circuit during an ESD event.

Abstract: An ESD power clamp circuit and method of ESD protection. The ESD power clamp circuit includes: a power clamp device coupled to a resistive/capacitive (RC) network, the RC network including a capacitor as the capacitive element of the RC network and one or more junction field effect transistors (JFETs) configured as variable resistors as the resistive element of the RC network.

Abstract: An enhanced turn-on time SCR based electrostatic discharge (ESD) protection circuit includes an integrated JFET, method of use and design structure. The enhanced turn-on time silicon controlled rectifier (SCR) based electrostatic discharge (ESD) protection circuit includes an integrated JFET in series with an NPN base.

Abstract: An electrostatic discharge protection device, methods of fabricating an electrostatic discharge protection device, and design structures for an electrostatic discharge protection device. A drain of a first field-effect transistor and a diffusion resistor of higher electrical resistance may be formed as different portions of a doped region. The diffusion resistor, which is directly coupled with the drain of the first field-effect transistor, may be defined using an isolation region of dielectric material disposed in the doped region and selective silicide formation. The electrostatic discharge protection device may also include a second field-effect transistor having a drain as a portion the doped region that is directly coupled with the diffusion resistor and indirectly coupled by the diffusion resistor with the drain of the first field-effect transistor.

Abstract: A semiconductor circuit for electric overstress (EOS) protection is provided. The semiconductor circuit employs an electrostatic discharge (ESD) protection circuit, which has a resistor-capacitor (RC) time-delay network connected to a discharge capacitor. An electronic component that has voltage snapback property or a diodic behavior is connected to alter the logic state of the gate of the discharge transistor under an EOS event. Particularly, the electronic component is configured to turn on the gate of the discharge capacitor throughout the duration of an electrical overstress (EOS) condition as well as throughout the duration of an ESD event. A design structure may be employed to design or manufacture a semiconductor circuit that provides protection against an EOS condition without time limitation, i.e., without being limited by the time constant of the RC time delay network for EOS events that last longer than 1 microsecond.

Abstract: An electrostatic discharge protection device, methods of fabricating an electrostatic discharge protection device, and design structures for an electrostatic discharge protection device. A drain of a first field-effect transistor and a diffusion resistor of higher electrical resistance may be formed as different portions of a doped region. The diffusion resistor, which is directly coupled with the drain of the first field-effect transistor, may be defined using an isolation region of dielectric material disposed in the doped region and selective silicide formation. The electrostatic discharge protection device may also include a second field-effect transistor having a drain as a portion the doped region that is directly coupled with the diffusion resistor and indirectly coupled by the diffusion resistor with the drain of the first field-effect transistor.

Abstract: A vertical NPNP structure fabricated using a triple well CMOS process, as well as methods of making the vertical NPNP structure, methods of providing electrostatic discharge (ESD) protection, and design structures for a BiCMOS integrated circuit. The vertical NPNP structure may be used to provide on-chip protection to an input/output (I/O) pad from negative-voltage ESD events. A vertical PNPN structure may be also used to protect the same I/O pad from positive-voltage ESD events.

Abstract: An electrostatic discharge (ESD) protection device for an integrated circuit includes a buried layer of a first polarity type formed in a substrate of a second polarity type. A well region of the second polarity type is formed above the buried layer. An FET of the first polarity type is formed within the well region. An inner pair of shallow wells of the first polarity type is disposed adjacent to source and drain diffusion regions of the FET, the inner pair of shallow wells having a depth such that a bottom of the inner pair of shallow wells is above a top of the buried layer. An outer pair of deep wells of the first polarity type extends down to the top of the buried layer such that the outer pair of deep wells and the buried layer define a perimeter of the well region of the second polarity type.

Abstract: An electrostatic discharge (ESD) protection circuit, methods of fabricating an ESD protection circuit, methods of providing ESD protection, and design structures for an ESD protection circuit. An NFET may be formed in a p-well and a PFET may be formed in an n-well. A butted p-n junction formed between the p-well and n-well results in an NPNP structure that forms an SCR integrated with the NFET and PFET. The NFET, PFET and SCR are configured to collectively protect a pad, such as a power pad, from ESD events. During normal operation, the NFET, PFET, and SCR are biased by an RC-trigger circuit so that the ESD protection circuit is in a high impedance state. During an ESD event while the chip is unpowered, the RC-trigger circuit outputs trigger signals that cause the SCR, NFET, and PFET to enter into conductive states and cooperatively to shunt ESD currents away from the protected pad.

Abstract: An ESD power clamp circuit and method of ESD protection. The ESD power clamp circuit includes: a power clamp device coupled to a resistive/capacitive (RC) network, the RC network including a capacitor as the capacitive element of the RC network and one or more junction field effect transistors (JFETs) configured as variable resistors as the resistive element of the RC network.

Abstract: A vertical NPNP structure fabricated using a triple well CMOS process, as well as methods of making the vertical NPNP structure, methods of providing electrostatic discharge (ESD) protection, and design structures for a BiCMOS integrated circuit. The vertical NPNP structure may be used to provide on-chip protection to an input/output (I/O) pad from negative-voltage ESD events. A vertical PNPN structure may be also used to protect the same I/O pad from positive-voltage ESD events.

Abstract: An integrated circuit, design structures and methods of forming the integrated circuit which includes a signal pad ESD coupled to an I/O signal pad and a power supply ESD coupled to a source VDD. The signal pad ESD and the power supply ESD are integrated in a single ESD structure.