Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate, where a top portion of the fin comprises a layer stack that includes alternating layers of a first semiconductor material and a second semiconductor material; forming a dummy gate structure over the fin; forming openings in the fin on opposing sides of the dummy gate structure; forming source/drain regions in the openings; removing the dummy gate structure to expose the first semiconductor material and the second semiconductor material under the dummy gate structure; performing a first etching process to selectively remove the exposed first semiconductor material, where after the first etching process, the exposed second semiconductor material form nanostructures, where each of the nanostructures has a first shape; and after the first etching process, performing a second etching process to reshape each of the nanostructures into a second shape different from the first shape.

Abstract: Provided are multi-gate devices and methods for fabricating such devices. An exemplary method includes forming gate structures over a semiconductor material, wherein the gate structures include a long channel (LC) gate structure and a short channel (SC) gate structure; forming a patterned mask over the semiconductor material, wherein the LC gate structure and the SC gate structure are not covered by the patterned mask; and performing an etch process on the LC gate structure and on the SC gate structure through the patterned mask to remove the LC gate structure and the SC gate structure, wherein removal of the LC gate structure forms a deep trench in the semiconductor substrate having a first depth, and wherein removal of the SC gate structure forms a shallow trench in the semiconductor substrate having a second depth less than the first depth.

Abstract: A method for fabricating semiconductor devices includes forming channel regions over a substrate. The channel regions, in parallel with one another, extend along a first lateral direction. Each channel region includes at least a respective pair of epitaxial structures. The method includes forming a gate structure over the channel regions, wherein the gate structure extends along a second lateral direction. The method includes removing, through a first etching process, a portion of the gate structure that was disposed over a first one of the channel regions. The method includes removing, through a second etching process, a portion of the first channel region. The second etching process includes one silicon etching process and one silicon oxide deposition process. The method includes removing, through a third etching process controlled based on a pulse signal, a portion of the substrate that was disposed below the removed portion of the first channel region.

Abstract: A method includes fabricating a semiconductor device, wherein the method includes depositing a coating layer on a first region and a second region under a loading condition such that a height of the coating layer in the first region is greater than a height of the coating layer in the second region. The method also includes applying processing gas to the coating layer to remove an upper portion of the coating layer such that a height of the coating layer in the first region is a same as a height of the coating layer in the second region.

Abstract: A semiconductor structure includes a substrate, a multi-gate FET device disposed over the substrate, a first isolation disposed in the substrate, and a second isolation disposed in the substrate. The multi-gate FET device includes a gate structure and epitaxial source/drain structures disposed at two sides of the gate structure. The first isolation includes a first portion and a second portion over the first portion. A top surface of the second portion is aligned with a top surface of the epitaxial source/drain structures. A width of the second portion is different from a width of the first portion.

Abstract: A semiconductor device includes a first channel region extending in a first lateral direction, and comprising a first epitaxial structure; a dielectric structure extending in a second lateral direction and disposed next to the first epitaxial structure; a plurality of first semiconductor sections interposed between a first sidewall of the dielectric structure and the first epitaxial structure; and a plurality of first dielectric sections interposed between the first sidewall of the dielectric structure and the first epitaxial structure. The first dielectric sections are alternately arranged with the first semiconductor sections. The dielectric structure has a second sidewall opposite to the first sidewall in the first lateral direction. A maximum variance percentage of a distance between the first sidewall and second sidewall is less than about 50%.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first channel region disposed over a substrate, a second channel region disposed adjacent the first channel region, a gate electrode layer disposed in the first and second channel regions, and a first dielectric feature disposed adjacent the gate electrode layer. The first dielectric feature includes a first dielectric material having a first thickness. The structure further includes a second dielectric feature disposed between the first and second channel regions, and the second dielectric feature includes a second dielectric material having a second thickness substantially less than the first thickness. The second thickness ranges from about 1 nm to about 20 nm.

Abstract: A method includes fabricating a semiconductor device, wherein the method includes depositing a coating layer on a first region and a second region under a loading condition such that a height of the coating layer in the first region is greater than a height of the coating layer in the second region. The method also includes applying processing gas to the coating layer to remove an upper portion of the coating layer such that a height of the coating layer in the first region is a same as a height of the coating layer in the second region.

Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate, where a top portion of the fin comprises a layer stack that includes alternating layers of a first semiconductor material and a second semiconductor material; forming a dummy gate structure over the fin; forming openings in the fin on opposing sides of the dummy gate structure; forming source/drain regions in the openings; removing the dummy gate structure to expose the first semiconductor material and the second semiconductor material under the dummy gate structure; performing a first etching process to selectively remove the exposed first semiconductor material, where after the first etching process, the exposed second semiconductor material form nanostructures, where each of the nanostructures has a first shape; and after the first etching process, performing a second etching process to reshape each of the nanostructures into a second shape different from the first shape.

Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate, where a top portion of the fin comprises a layer stack that includes alternating layers of a first semiconductor material and a second semiconductor material; forming a dummy gate structure over the fin; forming openings in the fin on opposing sides of the dummy gate structure; forming source/drain regions in the openings; removing the dummy gate structure to expose the first semiconductor material and the second semiconductor material under the dummy gate structure; performing a first etching process to selectively remove the exposed first semiconductor material, where after the first etching process, the exposed second semiconductor material form nanostructures, where each of the nanostructures has a first shape; and after the first etching process, performing a second etching process to reshape each of the nanostructures into a second shape different from the first shape.

Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate, where a top portion of the fin comprises a layer stack that includes alternating layers of a first semiconductor material and a second semiconductor material; forming a dummy gate structure over the fin; forming openings in the fin on opposing sides of the dummy gate structure; forming source/drain regions in the openings; removing the dummy gate structure to expose the first semiconductor material and the second semiconductor material under the dummy gate structure; performing a first etching process to selectively remove the exposed first semiconductor material, where after the first etching process, the exposed second semiconductor material form nanostructures, where each of the nanostructures has a first shape; and after the first etching process, performing a second etching process to reshape each of the nanostructures into a second shape different from the first shape.

Abstract: A method of fabricating a semiconductor device includes etching a substrate to form a plurality of first trenches and a plurality of second trenches performed at an electrostatic chuck (ESC) temperature between about 90° C. to 120° C. in the substrate, wherein each trench of the plurality of first trenches extends downward from the substrate major surface to a first height, and each trench of the plurality of second trenches extends downward from the substrate major surface to a second height greater than the first height. The method includes forming a first isolation structure in each of the plurality of first trenches. The method includes forming a second isolation structure in each of the plurality of second trenches, wherein a difference between a height of the first isolation structure and the first height equals a difference between a height of the second isolation structure and the second height.

Abstract: The disclosure relates to a method of fabricating a semiconductor device including forming a patterned hardmask layer over a substrate comprising a major surface. The method further includes forming a plurality of first trenches and a plurality of second trenches performed at an electrostatic chuck (ESC) temperature between about 90° C. to 120° C. in the substrate. The plurality of first trenches have a first width and extend downward from the substrate major surface to a first height, and the plurality of second trenches have a second width less than first width and extend downward from the substrate major surface to a second height greater than the first height.

Abstract: A method of fabricating a semiconductor device includes etching a substrate to form a plurality of first trenches and a plurality of second trenches performed at an electrostatic chuck (ESC) temperature between about 90° C. to 120° C. in the substrate, wherein each trench of the plurality of first trenches extends downward from the substrate major surface to a first height, and each trench of the plurality of second trenches extends downward from the substrate major surface to a second height greater than the first height. The method includes forming a first isolation structure in each of the plurality of first trenches. The method includes forming a second isolation structure in each of the plurality of second trenches, wherein a difference between a height of the first isolation structure and the first height equals a difference between a height of the second isolation structure and the second height.

Abstract: The disclosure relates to a method of fabricating a semiconductor device including forming a patterned hardmask layer over a substrate comprising a major surface. The method further includes forming a plurality of first trenches and a plurality of second trenches performed at an electrostatic chuck (ESC) temperature between about 90° C. to 120° C. in the substrate. The plurality of first trenches have a first width and extend downward from the substrate major surface to a first height, and the plurality of second trenches have a second width less than first width and extend downward from the substrate major surface to a second height greater than the first height.

Abstract: The disclosure relates to a fin field effect transistor (FinFET). An exemplary structure for a FinFET comprises a substrate comprising a major surface; a plurality of first trenches having a first width and extending downward from the substrate major surface to a first height, wherein a first space between adjacent first trenches defines a first fin; and a plurality of second trenches having a second width less than first width and extending downward from the substrate major surface to a second height greater than the first height, wherein a second space between adjacent second trenches defines a second fin.

Abstract: The disclosure relates to a fin field effect transistor (FinFET). An exemplary structure for a FinFET comprises a substrate comprising a major surface; a plurality of first trenches having a first width and extending downward from the substrate major surface to a first height, wherein a first space between adjacent first trenches defines a first fin; and a plurality of second trenches having a second width less than first width and extending downward from the substrate major surface to a second height greater than the first height, wherein a second space between adjacent second trenches defines a second fin.