Patents by Inventor Shunichi IGAHARA
Shunichi IGAHARA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220130462Abstract: According to one embodiment, the semiconductor memory medium includes a first memory cell, a first word line coupled to the first memory cell, and a row decoder coupled to the first word line. A write operation is executed multiple times on the first memory cell within a first period from after an execution of an erase operation to an execution of a next erase operation. The write operation includes at least one of program loops each including a program operation and a verify operation. In the verify operation, the row decoder applies a verify voltage to the first word line. The verify voltage is set in accordance with a number of executed write operations on the first memory cell within the first period.Type: ApplicationFiled: January 10, 2022Publication date: April 28, 2022Applicant: Kioxia CorporationInventors: Suguru NISHIKAWA, Takehiko AMAKI, Yoshihisa KOJIMA, Shunichi IGAHARA
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Publication number: 20220058085Abstract: A memory system includes a non-volatile memory and a controller that includes a toggle encoder configured to encode first data having a first bit length and a first number of toggles, into second data having a second bit length longer than the first bit length and a second number of toggles smaller than the first number of toggles, and transmit the second data to the non-volatile memory. The memory system may further include a toggle decoder configured to decode third data received from the non-volatile memory into fourth data, the third data having the second bit length and the second number of toggles and the fourth data having the first bit length and the first number of toggles.Type: ApplicationFiled: November 4, 2021Publication date: February 24, 2022Inventors: Shunichi IGAHARA, Yoshihisa KOJIMA, Takehiko AMAKI, Suguru NISHIKAWA
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Publication number: 20220051736Abstract: A memory system comprises a nonvolatile memory having a plurality of memory cells and a memory controller for controlling the nonvolatile memory. The plurality of memory cells is divided into different groups, and each group is assigned a threshold read count value from a predetermined range of read count values. The memory controller includes a counter which tracks a read count for each group, a determination circuit configured to compare the read count for each group tracked by the counter to the assigned threshold read count value for the group, and a nonvolatile memory read/write circuit configured to read data from the group when the determination circuit indicates the read count for the group has reached the assigned threshold read count value.Type: ApplicationFiled: October 27, 2021Publication date: February 17, 2022Inventors: Shigehiro ASANO, Neil Buxton, Julien Margetts, Shunichi Igahara, Takehiko Amaki
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Patent number: 11244728Abstract: According to one embodiment, the semiconductor memory medium includes a first memory cell, a first word line coupled to the first memory cell, and a row decoder coupled to the first word line. A write operation is executed multiple times on the first memory cell within a first period from after an execution of an erase operation to an execution of a next erase operation. The write operation includes at least one of program loops each including a program operation and a verify operation. In the verify operation, the row decoder applies a verify voltage to the first word line. The verify voltage is set in accordance with a number of executed write operations on the first memory cell within the first period.Type: GrantFiled: September 11, 2020Date of Patent: February 8, 2022Assignee: Kioxia CorporationInventors: Suguru Nishikawa, Takehiko Amaki, Yoshihisa Kojima, Shunichi Igahara
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Patent number: 11194656Abstract: A memory system includes a non-volatile memory and a controller that includes a toggle encoder configured to encode first data having a first bit length and a first number of toggles, into second data having a second bit length longer than the first bit length and a second number of toggles smaller than the first number of toggles, and transmit the second data to the non-volatile memory. The memory system may further include a toggle decoder configured to decode third data received from the non-volatile memory into fourth data, the third data having the second bit length and the second number of toggles and the fourth data having the first bit length and the first number of toggles.Type: GrantFiled: January 28, 2020Date of Patent: December 7, 2021Assignee: KIOXIA CORPORATIONInventors: Shunichi Igahara, Yoshihisa Kojima, Takehiko Amaki, Suguru Nishikawa
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Patent number: 11189353Abstract: A memory system comprises a nonvolatile memory having a plurality of memory cells and a memory controller for controlling the nonvolatile memory. The plurality of memory cells is divided into different groups, and each group is assigned a threshold read count value from a predetermined range of read count values. The memory controller includes a counter which tracks a read count for each group, a determination circuit configured to compare the read count for each group tracked by the counter to the assigned threshold read count value for the group, and a nonvolatile memory read/write circuit configured to read data from the group when the determination circuit indicates the read count for the group has reached the assigned threshold read count value.Type: GrantFiled: October 1, 2020Date of Patent: November 30, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Shigehiro Asano, Neil Buxton, Julien Margetts, Shunichi Igahara, Takehiko Amaki
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Publication number: 20210286671Abstract: According to one embodiment, a memory system includes a nonvolatile memory, a random access memory and a controller. When writing n?1 data portions of a first unit that are included in n?1 error correction code frames of a first size, respectively, in the nonvolatile memory, the controller generates a second error correction code that constitutes an error correction code frame of a second size together with the n?1 data portions of the first unit and a second data portion to be written into the nonvolatile memory by encoding the n?1 data portions of the first unit and the second data portion, and writes the second data portion and the second error correction code into the nonvolatile memory.Type: ApplicationFiled: March 11, 2021Publication date: September 16, 2021Applicant: Kioxia CorporationInventors: Takehiko AMAKI, Toshikatsu HIDA, Shunichi IGAHARA, Yoshihisa KOJIMA, Suguru NISHIKAWA
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Publication number: 20210257027Abstract: According to one embodiment, the semiconductor memory medium includes a first memory cell, a first word line coupled to the first memory cell, and a row decoder coupled to the first word line. A write operation is executed multiple times on the first memory cell within a first period from after an execution of an erase operation to an execution of a next erase operation. The write operation includes at least one of program loops each including a program operation and a verify operation. In the verify operation, the row decoder applies a verify voltage to the first word line. The verify voltage is set in accordance with a number of executed write operations on the first memory cell within the first period.Type: ApplicationFiled: September 11, 2020Publication date: August 19, 2021Applicant: Kioxia CorporationInventors: Suguru NISHIKAWA, Takehiko AMAKI, Yoshihisa KOJIMA, Shunichi IGAHARA
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Patent number: 11042310Abstract: A memory system includes a nonvolatile semiconductor memory including a first memory region for storing start-up information and a second memory region for storing a copy of the start-up information, a volatile semiconductor memory, and a controller. The controller is configured to determine whether or not an address of the second memory region is stored in the volatile semiconductor memory, issue a first start-up read command, which designates no read address, to the nonvolatile semiconductor memory to read the start-up information from the first memory region if the address of the second memory region is not stored in the volatile semiconductor memory, and issue a second start-up read command, which designates the address of the second memory region as a read address, to read the start-up information from the second memory region if the address of the second memory region is stored in the volatile semiconductor memory.Type: GrantFiled: July 9, 2019Date of Patent: June 22, 2021Assignee: KIOXIA CORPORATIONInventors: Riki Suzuki, Toshikatsu Hida, Takehiko Amaki, Shunichi Igahara
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Publication number: 20210073119Abstract: According to one embodiment, a memory system includes a non-volatile memory including first and second block groups, and a controller that performs a first write operation for the first block group and the first or a second write operation for the second block group. A first or second number of bits is written into a memory cell in the first or the second write operation. The second number of bits is larger than the first number of bits. The controller allocates a block to a buffer as a write destination block in the first write operation based on a degree of wear-out of at least one block, and writes data from an external device into the buffer in the first write operation.Type: ApplicationFiled: March 3, 2020Publication date: March 11, 2021Applicant: Kioxia CorporationInventors: Takehiko AMAKI, Toshikatsu HIDA, Shunichi IGAHARA, Yoshihisa KOJIMA, Suguru NISHIKAWA
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Publication number: 20210020253Abstract: A memory system comprises a nonvolatile memory having a plurality of memory cells and a memory controller for controlling the nonvolatile memory. The plurality of memory cells is divided into different groups, and each group is assigned a threshold read count value from a predetermined range of read count values. The memory controller includes a counter which tracks a read count for each group, a determination circuit configured to compare the read count for each group tracked by the counter to the assigned threshold read count value for the group, and a nonvolatile memory read/write circuit configured to read data from the group when the determination circuit indicates the read count for the group has reached the assigned threshold read count value.Type: ApplicationFiled: October 1, 2020Publication date: January 21, 2021Inventors: Shigehiro ASANO, Neil BUXTON, Julien MARGETTS, Shunichi IGAHARA, Takehiko AMAKI
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Publication number: 20210004169Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller electrically connected to the nonvolatile memory. The controller selects a write mode from a first mode in which data having N bits is written per one memory cell and a second mode in which data having M bits is written per one memory cell. N is equal to or larger than one. M is larger than N. The controller writes data into the nonvolatile memory in the selected write mode. The controller selects either the first mode or the second mode at least based on a total number of logical addresses mapped in a physical address space of the nonvolatile memory.Type: ApplicationFiled: September 22, 2020Publication date: January 7, 2021Applicant: TOSHIBA MEMORY CORPORATIONInventors: Shunichi Igahara, Toshikatsu Hida, Riki Suzuki, Takehiko Amaki, Suguru Nishikawa, Yoshihisa Kojima
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Publication number: 20200387425Abstract: A memory system includes a non-volatile memory and a controller that includes a toggle encoder configured to encode first data having a first bit length and a first number of toggles, into second data having a second bit length longer than the first bit length and a second number of toggles smaller than the first number of toggles, and transmit the second data to the non-volatile memory. The memory system may further include a toggle decoder configured to decode third data received from the non-volatile memory into fourth data, the third data having the second bit length and the second number of toggles and the fourth data having the first bit length and the first number of toggles.Type: ApplicationFiled: January 28, 2020Publication date: December 10, 2020Inventors: Shunichi IGAHARA, Yoshihisa KOJIMA, Takehiko AMAKI, Suguru NISHIKAWA
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Patent number: 10854302Abstract: A memory system comprises a nonvolatile memory having a plurality of memory cells and a memory controller for controlling the nonvolatile memory. The plurality of memory cells is divided into different groups, and each group is assigned a threshold read count value from a predetermined range of read count values. The memory controller includes a counter which tracks a read count for each group, a determination circuit configured to compare the read count for each group tracked by the counter to the assigned threshold read count value for the group, and a nonvolatile memory read/write circuit configured to read data from the group when the determination circuit indicates the read count for the group has reached the assigned threshold read count value.Type: GrantFiled: October 12, 2018Date of Patent: December 1, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Shigehiro Asano, Neil Buxton, Julien Margetts, Shunichi Igahara, Takehiko Amaki
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Patent number: 10824353Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller electrically connected to the nonvolatile memory. The controller selects a write mode from a first mode in which data having N bits is written per one memory cell and a second mode in which data having M bits is written per one memory cell. N is equal to or larger than one. M is larger than N. The controller writes data into the nonvolatile memory in the selected write mode. The controller selects either the first mode or the second mode at least based on a total number of logical addresses mapped in a physical address space of the nonvolatile memory.Type: GrantFiled: August 30, 2018Date of Patent: November 3, 2020Assignee: Toshiba Memory CorporationInventors: Shunichi Igahara, Toshikatsu Hida, Riki Suzuki, Takehiko Amaki, Suguru Nishikawa, Yoshihisa Kojima
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Publication number: 20200194075Abstract: A memory system includes a non-volatile memory having a plurality of memory cells, and a controller configured to carry out write operations in a first mode in which n-bit data is written per target memory cell of the non-volatile memory until an allowable data amount of data items has been written, and then, in a second mode in which m-bit data is written per target memory cell of the non-volatile memory, where n is an integer of one or more and m is an integer greater than n. The controller is further configured to detect that an idle state, in which a command has not been received from the host, has continued for a threshold period of time or more, increase the allowable data amount in response thereto, and after the increase, carry out a write operation to write data items in the non-volatile memory in the first mode.Type: ApplicationFiled: February 12, 2020Publication date: June 18, 2020Inventors: Shunichi IGAHARA, Toshikatsu HIDA
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Patent number: 10614888Abstract: A memory system includes a non-volatile memory having a plurality of memory cells, and a controller configured to carry out write operations in a first mode in which n-bit data is written per target memory cell of the non-volatile memory until an allowable data amount of data items has been written, and then, in a second mode in which m-bit data is written per target memory cell of the non-volatile memory, where n is an integer of one or more and m is an integer greater than n. The controller is further configured to detect that an idle state, in which a command has not been received from the host, has continued for a threshold period of time or more, increase the allowable data amount in response thereto, and after the increase, carry out a write operation to write data items in the non-volatile memory in the first mode.Type: GrantFiled: January 22, 2018Date of Patent: April 7, 2020Assignee: Toshiba Memory CorporationInventors: Shunichi Igahara, Toshikatsu Hida
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Publication number: 20190332285Abstract: A memory system includes a nonvolatile semiconductor memory including a first memory region for storing start-up information and a second memory region for storing a copy of the start-up information, a volatile semiconductor memory, and a controller. The controller is configured to determine whether or not an address of the second memory region is stored in the volatile semiconductor memory, issue a first start-up read command, which designates no read address, to the nonvolatile semiconductor memory to read the start-up information from the first memory region if the address of the second memory region is not stored in the volatile semiconductor memory, and issue a second start-up read command, which designates the address of the second memory region as a read address, to read the start-up information from the second memory region if the address of the second memory region is stored in the volatile semiconductor memory.Type: ApplicationFiled: July 9, 2019Publication date: October 31, 2019Inventors: Riki SUZUKI, Toshikatsu HIDA, Takehiko AMAKI, Shunichi IGAHARA
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Patent number: 10437490Abstract: A memory system includes a nonvolatile semiconductor memory including a first memory region for storing start-up information and a second memory region for storing a copy of the start-up information, a volatile semiconductor memory, and a controller. The controller is configured to determine whether or not an address of the second memory region is stored in the volatile semiconductor memory, issue a first start-up read command, which designates no read address, to the nonvolatile semiconductor memory to read the start-up information from the first memory region if the address of the second memory region is not stored in the volatile semiconductor memory, and issue a second start-up read command, which designates the address of the second memory region as a read address, to read the start-up information from the second memory region if the address of the second memory region is stored in the volatile semiconductor memory.Type: GrantFiled: October 18, 2017Date of Patent: October 8, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Riki Suzuki, Toshikatsu Hida, Takehiko Amaki, Shunichi Igahara
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Publication number: 20190287632Abstract: A memory system comprises a nonvolatile memory having a plurality of memory cells and a memory controller for controlling the nonvolatile memory. The plurality of memory cells is divided into different groups, and each group is assigned a threshold read count value from a predetermined range of read count values. The memory controller includes a counter which tracks a read count for each group, a determination circuit configured to compare the read count for each group tracked by the counter to the assigned threshold read count value for the group, and a nonvolatile memory read/write circuit configured to read data from the group when the determination circuit indicates the read count for the group has reached the assigned threshold read count value.Type: ApplicationFiled: October 12, 2018Publication date: September 19, 2019Inventors: Shigehiro ASANO, Neil BUXTON, Julien MARGETTS, Shunichi IGAHARA, Takehiko AMAKI