Patents by Inventor Shunichi Nagashima

Shunichi Nagashima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240184467
    Abstract: Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several sets of latencies (e.g., read, write, or write recovery latencies), and the memory device or system may apply a set of latencies depending on which features of the memory device are enabled. For example, control circuitry may be configured to enable one or more features during operations on a memory array, and the control circuitry may apply a set of latency values based on a number or type of features that are enabled. The sets of latency values may depend, for example, on whether various control features (e.g., dynamic voltage frequency scaling) are enabled, and a device may operate within certain frequency ranges irrespective of other characteristics (e.g., mode register values) or latencies applied.
    Type: Application
    Filed: February 16, 2024
    Publication date: June 6, 2024
    Inventors: Dean D. Gans, Yoshiro Riho, Shunichi Saito, Osamu Nagashima
  • Publication number: 20240085110
    Abstract: To ensure stable supply of a cold iron source to a melting chamber, a method of producing molten iron uses an electric furnace that includes: a preheating chamber; a melting chamber; an extruder located in the preheating chamber; and a video device configured to observe an inside of the melting chamber, and comprises: an extrusion process of supplying a cold iron source preheated in the preheating chamber to the melting chamber by the extruder; and a melting process of melting the cold iron source supplied to the melting chamber by arc heat to obtain molten iron, wherein in the extrusion process, a moving amount of the extruder and/or a time interval for moving the extruder is controlled based on visual information obtained from the video device.
    Type: Application
    Filed: January 27, 2022
    Publication date: March 14, 2024
    Applicant: JFE STEEL CORPORATION
    Inventors: Koichi TSUTSUMI, Yoshihiro MIWA, Shohei NAGASHIMA, Goro OKUYAMA, Katsutoshi ENDO, Shunichi KAWANAMI
  • Publication number: 20240078173
    Abstract: A training operation may be performed by a memory controller to provide a system clock signal and a data clock signal having a desired temporal (e.g., phase) relationship to one another. The system clock and data clock signals may be provided to a memory. In some examples, the memory controller may provide a command to the memory to put the memory in a training mode. Once in the training mode, the memory controller may provide a write command and toggle the data clock signal a number of times. If the memory provides one output, the memory controller may adjust the relationship between the data clock and system clock signals. If the memory provides another output, the memory controller may maintain the relationship between the data clock and system clock signals and exit the training mode.
    Type: Application
    Filed: July 17, 2023
    Publication date: March 7, 2024
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: OSAMU NAGASHIMA, YOSHINORI MATSUI, KEUN SOO SONG, HIROKI TAKAHASHI, SHUNICHI SAITO
  • Patent number: 11914874
    Abstract: Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several sets of latencies (e.g., read, write, or write recovery latencies), and the memory device or system may apply a set of latencies depending on which features of the memory device are enabled. For example, control circuitry may be configured to enable one or more features during operations on a memory array, and the control circuitry may apply a set of latency values based on a number or type of features that are enabled. The sets of latency values may depend, for example, on whether various control features (e.g., dynamic voltage frequency scaling) are enabled, and a device may operate within certain frequency ranges irrespective of other characteristics (e.g., mode register values) or latencies applied.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: February 27, 2024
    Inventors: Dean D. Gans, Yoshiro Riho, Shunichi Saito, Osamu Nagashima
  • Patent number: 11020835
    Abstract: A parts supply apparatus includes a supply tray stacking portion where a supply tray containing parts is stacked; a tray raising/lowering unit for separating one of the supply trays from the supply tray stacking portion; a tray holding unit with which the tray raising/lowering unit is provided; and an empty tray stacking portion where an empty tray, which is the supply tray that is emptied after supply of the parts, is stacked. The empty tray stacking portion is disposed above the supply tray stacking portion in a vertical direction.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: June 1, 2021
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hiroshi Sasamoto, Shunichi Nagashima
  • Publication number: 20180318975
    Abstract: A parts supply apparatus includes a supply tray stacking portion where a supply tray containing parts is stacked; a tray raising/lowering unit for separating one of the supply trays from the supply tray stacking portion; a tray holding unit with which the tray raising/lowering unit is provided; and an empty tray stacking portion where an empty tray, which is the supply tray that is emptied after supply of the parts, is stacked. The empty tray stacking portion is disposed above the supply tray stacking portion in a vertical direction.
    Type: Application
    Filed: July 13, 2018
    Publication date: November 8, 2018
    Inventors: Hiroshi Sasamoto, Shunichi Nagashima
  • Patent number: 10076815
    Abstract: A parts supply apparatus includes a supply tray stacking portion where a supply tray containing parts is stacked; a tray raising/lowering unit for separating one of the supply trays from the supply tray stacking portion; a tray holding unit with which the tray raising/lowering unit is provided; and an empty tray stacking portion where an empty tray, which is the supply tray that is emptied after supply of the parts, is stacked. The empty tray stacking portion is disposed above the supply tray stacking portion in a vertical direction.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: September 18, 2018
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hiroshi Sasamoto, Shunichi Nagashima
  • Publication number: 20160297612
    Abstract: A parts supply apparatus includes a supply tray stacking portion where a supply tray containing parts is stacked; a tray raising/lowering unit for separating one of the supply trays from the supply tray stacking portion; a tray holding unit with which the tray raising/lowering unit is provided; and an empty tray stacking portion where an empty tray, which is the supply tray that is emptied after supply of the parts, is stacked. The empty tray stacking portion is disposed above the supply tray stacking portion in a vertical direction.
    Type: Application
    Filed: April 5, 2016
    Publication date: October 13, 2016
    Inventors: Hiroshi Sasamoto, Shunichi Nagashima
  • Patent number: 6162320
    Abstract: A method is provided for laminating polyolefin resins, which includes placing a plurality of polyolefin resin films or sheets one upon another and sealing the adjacent surfaces of the films or sheets by high-frequency dielectric heating while being pressed between a mold and a level block, and which is further characterized in the claims. The method of the present invention yields sealed polyolefin resin articles having high mechanical strength and good transparency at the sealed site.
    Type: Grant
    Filed: March 10, 1999
    Date of Patent: December 19, 2000
    Assignee: Idemitsu Petrochemical Co., Ltd.
    Inventors: Tomohiro Nagao, Shunichi Nagashima, Kenichi Fujiwara