Patents by Inventor Shunichi SENO

Shunichi SENO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230413516
    Abstract: A semiconductor memory device includes: a first wiring; a first semiconductor layer connected to the first wiring, the first semiconductor layer; a first electrode, the first electrode being connected to the first semiconductor layer; a second electrode disposed between the first electrode and the first wiring, the second electrode being opposed to the first semiconductor layer; a third electrode disposed between the second electrode and the first wiring, the third electrode; a second semiconductor layer disposed between the third electrode and the first semiconductor layer, the second semiconductor layer being opposed to the third electrode; and an electric charge accumulating layer electrically connected to the first wiring via the second semiconductor layer, the electric charge accumulating layer being opposed to the first semiconductor layer.
    Type: Application
    Filed: August 29, 2023
    Publication date: December 21, 2023
    Applicant: Kioxia Corporation
    Inventors: Teruhisa SONOHARA, Shunichi SENO, Hiroki TOKUHIRA, Fumitaka ARAI
  • Patent number: 11778808
    Abstract: A semiconductor memory device includes: a first wiring; a first semiconductor layer connected to the first wiring, the first semiconductor layer; a first electrode, the first electrode being connected to the first semiconductor layer; a second electrode disposed between the first electrode and the first wiring, the second electrode being opposed to the first semiconductor layer; a third electrode disposed between the second electrode and the first wiring, the third electrode; a second semiconductor layer disposed between the third electrode and the first semiconductor layer, the second semiconductor layer being opposed to the third electrode; and an electric charge accumulating layer electrically connected to the first wiring via the second semiconductor layer, the electric charge accumulating layer being opposed to the first semiconductor layer.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: October 3, 2023
    Assignee: Kioxia Corporation
    Inventors: Teruhisa Sonohara, Shunichi Seno, Hiroki Tokuhira, Fumitaka Arai
  • Publication number: 20220328489
    Abstract: A semiconductor memory device includes: a first wiring; a first semiconductor layer connected to the first wiring, the first semiconductor layer; a first electrode, the first electrode being connected to the first semiconductor layer; a second electrode disposed between the first electrode and the first wiring, the second electrode being opposed to the first semiconductor layer; a third electrode disposed between the second electrode and the first wiring, the third electrode; a second semiconductor layer disposed between the third electrode and the first semiconductor layer, the second semiconductor layer being opposed to the third electrode; and an electric charge accumulating layer electrically connected to the first wiring via the second semiconductor layer, the electric charge accumulating layer being opposed to the first semiconductor layer.
    Type: Application
    Filed: September 13, 2021
    Publication date: October 13, 2022
    Applicant: Kioxia Corporation
    Inventors: Teruhisa SONOHARA, Shunichi SENO, Hiroki TOKUHIRA, Fumitaka ARAI