Patents by Inventor Shunichi Tokitoh
Shunichi Tokitoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8513778Abstract: Disclosed is a semiconductor device that is capable of preventing impurities such as moisture from being introduced into an active region at the time of dicing and at the time of bonding and that is capable of being easily miniaturized. The semiconductor device includes a cylindrical dummy wire having an opening for allowing a wire interconnecting a semiconductor element and an external connection terminal to pass therethrough, extending in an insulation film provided on a semiconductor layer having the semiconductor element to surround the semiconductor element, and disposed inside the external connection terminal.Type: GrantFiled: May 22, 2009Date of Patent: August 20, 2013Assignee: Oki Semiconductor Co., Ltd.Inventor: Shunichi Tokitoh
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Patent number: 7737474Abstract: A semiconductor device includes a substrate, on which an element region and a peripheral region are defined. At least one function element is to be provided in the element region, and the peripheral region surrounds the element region. The semiconductor device also includes a layer of wiring. The semiconductor device also includes a seal ring having a ring portion that is provided in the peripheral region in the same layer as the wiring layer. The ring portion has a main body surrounding a chip region, and a plurality of portions protruding toward the element region from the seal ring main body.Type: GrantFiled: October 31, 2007Date of Patent: June 15, 2010Assignee: Oki Semiconductor Co., Ltd.Inventor: Shunichi Tokitoh
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Patent number: 7675175Abstract: A semiconductor device with a damascene wiring structure which can prevent short-circuits between a seal ring and a wiring line or electrode pad. An upper layer barrier layer made from a conductive barrier material film is formed on an interlayer insulating film groove sidewall of the semiconductor device. Embedded in the groove is an upper layer seal ring wiring line with thickness of approximately 10 micrometers for instance, in which a plurality of isolated pockets of insulators are disbursed. These isolated pockets of insulators are formed using the interlayer insulating film which forms the damascene wiring line. Additionally, a first upper layer groove wiring line and a second upper layer groove wiring line are formed in an element forming region, and an upper layer barrier layer is formed on the outside perimeter. The upper layer seal ring wiring line and both upper layer wiring lines all have damascene wiring structures.Type: GrantFiled: June 13, 2005Date of Patent: March 9, 2010Assignee: Oki Semiconductor Co., Ltd.Inventors: Shunichi Tokitoh, Seiichi Kondou, Bo Un Yoon
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Publication number: 20090315184Abstract: Disclosed is a semiconductor device that is capable of preventing impurities such as moisture from being introduced into an active region at the time of dicing and at the time of bonding and that is capable of being easily miniaturized. The semiconductor device includes a cylindrical dummy wire having an opening for allowing a wire interconnecting a semiconductor element and an external connection terminal to pass therethrough, extending in an insulation film provided on a semiconductor layer having the semiconductor element to surround the semiconductor element, and disposed inside the external connection terminal.Type: ApplicationFiled: May 22, 2009Publication date: December 24, 2009Applicant: OKI SEMICONDUCTOR CO., LTD.Inventor: Shunichi Tokitoh
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Patent number: 7560378Abstract: A diffusion barrier film, a second insulating film, and a cap film are sequentially laminated on a first insulating film over a substrate. A wiring trench portion is formed extending therethrough to the first insulating film, assuming that the ratio of a width of the wiring trench portion in a direction orthogonal to its extending direction to a height of the wiring trench portion is 2.8 times even at a maximum. A barrier metal film is formed to cover the cap film and the wiring trench portion. A wiring film is deposited to cover the barrier metal film. The wiring film and the barrier metal film are chipped away until the surface of the cap film is exposed from the surface of the wiring film, thereby to form a wiring portion which buries the wiring trench portion.Type: GrantFiled: August 10, 2006Date of Patent: July 14, 2009Assignee: Oki Semiconductor Co., Ltd.Inventor: Shunichi Tokitoh
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Publication number: 20090008750Abstract: A semiconductor device having a seal ring structure with high stress resistance is provided. The semiconductor device is provided with a semiconductor layer including a plurality of semiconductor elements, an insulating film formed on the semiconductor layer, and a body that passes through the insulating film and surrounds the semiconductor elements as a whole. The body includes a plurality of walls that are spaced apart from each other in a circumferential direction and are arranged in parallel with one another, and a plurality of bridges, each of which intersects at least one of the plurality of walls.Type: ApplicationFiled: June 20, 2008Publication date: January 8, 2009Inventor: Shunichi Tokitoh
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Publication number: 20080157285Abstract: A semiconductor device includes a substrate, on which an element region and a peripheral region are defined. At least one function element is to be provided in the element region, and the peripheral region surrounds the element region. The semiconductor device also includes a layer of wiring. The semiconductor device also includes a seal ring having a ring portion that is provided in the peripheral region in the same layer as the wiring layer. The ring portion has a main body surrounding a chip region, and a plurality of portions protruding toward the element region from the seal ring main body.Type: ApplicationFiled: October 31, 2007Publication date: July 3, 2008Applicant: Oki Electric Industry Co., Ltd.Inventor: Shunichi Tokitoh
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Patent number: 7309899Abstract: A semiconductor device includes a semiconductor substrate, a gate insulating layer, a gate electrode structure and a side wall structure. The gate insulating layer is formed on the semiconductor substrate. The gate electrode structure is formed on the gate insulating layer, and includes a lower gate electrode layer and a cap gate layer. The side wall structure includes a nitride side wall spacer, and an oxide layer formed between the semiconductor substrate and the nitride side wall spacer and between the lower gate electrode layer and the nitride side wall spacer. A thickness of the oxide layer is greater than a thickness of the gate insulating layer, so as to prevent diffusion of nitrogen from the nitride side wall spacer to the semiconductor substrate. A height of the gate electrode structure is substantially equal to a height of the side wall structure after completion of the semiconductor device.Type: GrantFiled: November 19, 2004Date of Patent: December 18, 2007Assignee: Oki Electric Industry Co., Ltd.Inventors: Masahiro Yoshida, Shunichi Tokitoh
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Publication number: 20070042590Abstract: A diffusion barrier film which covers the surface of a first insulating film provided on an upper surface of a semiconductor substrate, a second insulating film which covers over the diffusion barrier film, and a cap film which covers the second insulating film, are sequentially laminated. A wiring trench portion, which extends through the diffusion barrier film, the second insulating film and the cap film, is formed assuming that the ratio of a width of the wiring trench portion lying in the direction orthogonal to its extending direction to a height from a bottom face of the wiring trench portion to the surface of the cap film is 2.8 times even at a maximum. A barrier metal film, which covers the surface of the cap film and the surface of the wiring trench portion, is formed. A wiring film is deposited which covers over the barrier metal film.Type: ApplicationFiled: August 10, 2006Publication date: February 22, 2007Inventor: Shunichi Tokitoh
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Patent number: 7125794Abstract: A first CVD dielectric layer is deposited on a surface of a semiconductor substrate. Next, low-k layers are deposited in at least two different steps to form one of a via-layer dielectric film and a wiring-layer dielectric film on the first CVD dielectric layer. Immediately after the depositions, thermal treatment is performed. A second CVD dielectric layer is deposited on the low-k layers. A groove is formed in the second CVD dielectric layer and the low-k layers. A metal layer is deposited on that structure, filling the groove. The metal layer is removed from the second CVD dielectric layer by chemical mechanical polishing.Type: GrantFiled: September 15, 2004Date of Patent: October 24, 2006Assignee: Renesas Technology Corp.Inventors: Seiichi Kondo, Kaori Misawa, Shunichi Tokitoh, Takashi Nasuno
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Patent number: 7078303Abstract: A semiconductor device includes a semiconductor substrate, a silicon oxide layer formed on the semiconductor substrate, a gate electrode formed over the silicon oxide layer, and a side wall structure formed over the silicon oxide layer and adjacent the gate electrode. In one configuration, the thickness of the silicon oxide layer under the sidewall structure is thicker than the thickness of the silicon oxide layer under the gate electrode.Type: GrantFiled: May 25, 2005Date of Patent: July 18, 2006Assignee: Oki Electric Industry Co., Ltd.Inventors: Masahiro Yoshida, Shunichi Tokitoh
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Publication number: 20060001165Abstract: A semiconductor device with a damascene wiring structure which can prevent short-circuits between a seal ring and a wiring line or electrode pad. The upper layer barrier layer made from a conductive barrier material film is formed on the interlayer insulating film groove sidewall of the semiconductor device, an upper layer seal ring wiring line with the thickness of approximately 10 micrometers for instance made from a wiring material film is embedded in a groove, and a plurality of isolated pockets of insulators are formed to be disbursed in the upper layer seal ring wiring line. These isolated pockets of insulators formed using the interlayer insulating film which forms the aforementioned damascene wiring line. Furthermore, a first upper layer groove wiring line and a second upper layer groove wiring line are formed in the element forming region, and an upper layer barrier layer is formed on the outside perimeter.Type: ApplicationFiled: June 13, 2005Publication date: January 5, 2006Inventors: Shunichi Tokitoh, Seiichi Kondou, Bo Un Yoon
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Patent number: 6953732Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor substrate, and then forming a gate insulating layer on the semiconductor substrate. A lower gate electrode layer and a cap gate layer are formed on the gate insulating layer. The lower gate electrode layer and the cap gate layer are patterned to form a gate electrode structure. An LDD region is formed on the semiconductor substrate. An oxide layer is formed on the gate electrode structure and the semiconductor substrate. A thickness of the oxide layer is greater than a thickness of the gate insulating layer. Next, a nitride layer is formed on the oxide layer. Finally, the oxide layer and the nitride layer are etched to form a nitride sidewall spacer on the gate electrode structure through the oxide layer.Type: GrantFiled: January 23, 2004Date of Patent: October 11, 2005Assignee: Oki Electric Industry Co., Ltd.Inventors: Masahiro Yoshida, Shunichi Tokitoh
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Publication number: 20050221562Abstract: A semiconductor device includes a semiconductor substrate, a silicon oxide layer formed on the semiconductor substrate, a gate electrode formed over the silicon oxide layer, and a side wall structure formed over the silicon oxide layer and adjacent the gate electrode. In one configuration, the thickness of the silicon oxide layer under the sidewall structure is thicker than the thickness of the silicon oxide layer under the gate electrode.Type: ApplicationFiled: May 25, 2005Publication date: October 6, 2005Inventors: Masahiro Yoshida, Shunichi Tokitoh
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Publication number: 20050087799Abstract: A semiconductor device includes a semiconductor substrate, a gate insulating layer, a gate electrode structure and a side wall structure. The gate insulating layer is formed on the semiconductor substrate. The gate electrode structure is formed on the gate insulating layer, and includes a lower gate electrode layer and a cap gate layer. The side wall structure includes a nitride side wall spacer, and an oxide layer formed between the semiconductor substrate and the nitride side wall spacer and between the lower gate electrode layer and the nitride side wall spacer. A thickness of the oxide layer is greater than a thickness of the gate insulating layer, so as to prevent diffusion of nitrogen from the nitride side wall spacer to the semiconductor substrate. A height of the gate electrode structure is substantially equal to a height of the side wall structure after completion of the semiconductor device.Type: ApplicationFiled: November 19, 2004Publication date: April 28, 2005Inventors: Masahiro Yoshida, Shunichi Tokitoh
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Publication number: 20050064699Abstract: A first CVD dielectric layer is deposited on a surface of a semiconductor substrate. Next, low-k layers are deposited in at least two different steps to form one of a via-layer dielectric film and a wiring-layer dielectric film on the first CVD dielectric layer. Immediately after the depositions, thermal treatment is performed. A second CVD dielectric layer is deposited on the low-k layers. A groove is formed in the second CVD dielectric layer and the low-k layers. A metal layer is deposited on that structure, filling the groove. The metal layer is removed from the second CVD dielectric layer by chemical mechanical polishing.Type: ApplicationFiled: September 15, 2004Publication date: March 24, 2005Applicant: Semiconductor Leading Edge Technologies, Inc.Inventors: Seiichi Kondo, Kaori Misawa, Shunichi Tokitoh, Takashi Nasuno
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Publication number: 20040152275Abstract: A semiconductor device includes a semiconductor substrate, a silicon oxide layer formed on the semiconductor substrate, a gate electrode formed over the silicon oxide layer, and a side wall structure formed over the silicon oxide layer and adjacent the gate electrode. In one configuration, the thickness of the silicon oxide layer under the sidewall structure is thicker than the thickness of the silicon oxide layer under the gate electrode.Type: ApplicationFiled: January 23, 2004Publication date: August 5, 2004Inventors: Masahiro Yoshida, Shunichi Tokitoh
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Patent number: 6700167Abstract: A semiconductor device includes a semiconductor substrate, a silicon oxide layer formed on the semiconductor substrate, a gate electrode formed over the silicon oxide layer, and a side wall structure formed over the silicon oxide layer and adjacent the gate electrode. In one configuration, the thickness of the silicon oxide layer under the sidewall structure is thicker than the thickness of the silicon oxide layer under the gate electrode.Type: GrantFiled: December 17, 2002Date of Patent: March 2, 2004Assignee: Oki Electric Industry Co., Ltd.Inventors: Masahiro Yoshida, Shunichi Tokitoh
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Patent number: 6677651Abstract: A semiconductor device includes a semiconductor substrate, a silicon oxide layer formed on the semiconductor substrate, a gate electrode formed over the silicon oxide layer, and a side wall structure formed over the silicon oxide layer and adjacent the gate electrode. In one configuration, the thickness of the silicon oxide layer under the sidewall structure is thicker than the thickness of the silicon oxide layer under the gate electrode.Type: GrantFiled: December 17, 2002Date of Patent: January 13, 2004Assignee: Oki Electric Industry Co., Ltd.Inventors: Masahiro Yoshida, Shunichi Tokitoh
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Publication number: 20030085433Abstract: A semiconductor device includes a semiconductor substrate, a silicon oxide layer formed on the semiconductor substrate, a gate electrode formed over the silicon oxide layer, and a side wall structure formed over the silicon oxide layer and adjacent the gate electrode. In one configuration, the thickness of the silicon oxide layer under the sidewall structure is thicker than the thickness of the silicon oxide layer under the gate electrode.Type: ApplicationFiled: December 17, 2002Publication date: May 8, 2003Inventors: Masahiro Yoshida, Shunichi Tokitoh