Abstract: A database management system for executing database operations in parallel by a plurality of nodes and a query processing method are described. The database management system contains a decision management node for deciding a distribution node for retrieving information so as to analyze a query received from an application program, generate a processing procedure for processing the query, and execute the process, and a join node for sorting, merging, and joining the information retrieved by the distribution node. When the query process is executed, the distribution node decided by the decision management node retrieves the information to be processed and the join node decided by the decision management node also obtains the result for the query from the retrieved information. The query result is outputted from an output node and transferred to the application program.

Abstract: A text data registering and retrieving method capable of improving the transaction processing performance is provided. The document number of a document for which deletion or replacement has been newly requested is registered in an updated document number list. The text data of the document for which insertion or replacement has been newly requested is registered in an update text buffer. The text data stored temporarily in the update text buffer is registered in a plural-character occurrence file defining a text index in a character component file merge step. The data registered in the plural-character occurrence file is retrieved for query terms. The text data stored in the update text buffer is retrieved for the query terms. The document number of a document updated or deleted is deleted from the result of retrieval in the plural-character occurrence file. Also, the result or the document number obtained in the, update text buffer is added to the result of retrieval to provide a final retrieval result.

Abstract: A method and a system of database divisional management for use with a parallel database system comprising an FES (front end server), BES's (back end servers), an IOS (I/O server) and disk units. The numbers of processors assigned to the FES, BES's and IOS, the number of disk units, and the number of partitions of the disk units are determined in accordance with the load pattern in question. Illustratively, there may be established a configuration of one FES, four BES's, one IOS and eight disk units. The number of BES's is varied from one to four depending on the fluctuation in load, so that a scalable system configuration is implemented. When the number of BES's is increased or decreased, only the management information thereabout is transferred between nodes and not the data, whereby the desired degree of parallelism is obtained for high-speed query processing.

Abstract: A database management system for executing database operations in parallel by a plurality of nodes and a query processing method for it are described. The database management system contains a decision management node for deciding a distribution node for retrieving information so as to analyze a query received from an application program, generate a processing procedure for processing the query, and execute the process and a join node for sorting, merging, and joining the information retrieved by the distribution node. When the query process is executed, the distribution node decided by the decision management node retrieves the information to be processed and the join node decided by the decision management node also obtains the result for the query from the retrieved information. The query result is outputted from an output node and transferred to the application program.

Abstract: A fast access high capacity data storage system and method are disclosed, the data storage system including a disk-based storage system employing a plurality of storage surfaces. Selected storage surfaces have a plurality of independently controlled data access heads in data communication therewith, and circuitry is provided for allowing concurrent data transfers through the plurality of data access heads. Performance is further improved by monitoring frequently accessed data records and transferring them to a copy recording surface or recording surfaces less frequently used, and by moving a data access head of the plurality of data access heads to other recording surfaces to decrease access bottlenecks. The storage system further includes circuitry for averaging at least one of record length data, transfer timing data, access timing data and address data.

Abstract: A plurality of data banks operable independently from each other is controlled by a control circuit so that a set of received data signals are written into respective storage locations predetermined for respective data signals within respective data banks predetermined for respective data signals, wherein respective storage locations and respective data banks for respective received data signals are predetermined depending upon the arrival numbers of respective received data signals and a predetermined bank order, so that respective storage locations for two data signals received one after another belong to different data banks arranged according to the bank order. The data banks are controlled by the control circuit so that a set of data signals are read out according to the order of receipt of the set of data signals and from a timing before completion of the writing of the set under a condition that each data bank performs only one of write and read operations during a clock period.

Abstract: A data processor in which a plurality of address generator circuits corresponding to mutually different elements are provided for respective input vectors. Each address generator circuit updates an address upon waiting the arrival of data accessed by the address generator circuit. Also, access requests by respective address generator circuits are issued with a shift of one clock between an adjacent request. Therefore an access request is issued for data every cycle so as to completely fill each cycle of the complete process.

Abstract: In a data communication management system, a first transaction causes an application program to start. When a transaction arises, it is determined whether the transaction is to be batch processed as one of a plurality of transactions. Batch processing is determined based on the name of the transaction and the name of a application program requested. If it is determined that the transaction should not be batch processed, the transaction undergoes ordinary processing. If it is determined that the transaction is to be batch processed, the transaction is stored in a batch process queue. The application program for all transactions stored in the batch process queue is started when the number of transactions stored in the queue has exceeded a certain number or when a predetermined time length has elapsed after any transaction has been stored in the queue. After the application program is terminated, a batch synchronous point process is carried out for all the transactions.

Abstract: A method for controlling a vector processor so as to detect whether or not a value of each data signal among a first set of data signals has a specific relation with a value of one of a second set of data signals. The vector processor includes an operation unit for performing an arithmetical or logical operation in a pipeline manner on vector data. First and second vector data are formed each including groups of data signals related to the first and second set of data signals. The operation of the operation unit is controlled such that the operation unit detects whether or not a value of each data signal of the first vector data has a specific relation with a value of a corresponding data signal of the second vector data. Third vector data including result data signals is generated thereby which indicate the result of the operation.

Abstract: A vector processor includes a memory for storing vector data, a processing circuit, a fetch circuit for sequentially fetching elements of a first vector data to be processed from the memory and supplying them to the processing circuit, a generation circuit for generating tag information to designate the fetched vector elements, and a write circuit responsive to the process result by the processing means for writing the tag information generated for the element having a predetermined process result into the memory as one element of a second vector data.

Abstract: In an information processing method and system including a secondary storage, a primary storage for storing data blocks of the secondary storage and a directory containing control information for the data blocks stored in the primary storage, the directory is consulted to determine whether a desired data block is in the primary storage, and if it is, the data block is read from the primary storage. The control information of the directory contains pairs of addresses on the primary storage of the data blocks stored in the primary storage and the addresses on the secondary storage.

Abstract: A vector processor having a vector register made up of elements of l.sub.2 -byte size for storing vector data made up of a plurality of elements read out from a main storage which has a plurality of storage areas and is capable of reading out data of l.sub.1 -byte size beginning from a specified address bound, and adapted to write vector data with an element size of m (l.sub.1 /m is an integer and l.sub.2 is larger or equal to m) into the vector register sequentially, read-out vector data from the vector register for computation by an arithmetic unit, and write the computational result into the vector register, wherein the processor writes elements of vector data read out from the main storage into separatte, specified locations of the vector register in an order required for subsequent operations.

Abstract: A plurality of data bands operable independently from each other is controlled by a control circuit so that a set of received data signals are written into respective storage locations predetermined for respective data signals within respective data banks predetermined for respective data signals, wherein respective storage locations and respective data banks for respective received data signals are predetermined depending upon the arrival numbers of respective received data signals and a predetermined bank order, so that respective storage locations for two data signals received one after another belong to different data banks arranged according to the bank order. The data banks are controlled by the control circuit so that a set of data signals are read out according to the order of receipt of the set of data signals and from a timing before completion of the writing of the set under a condition that each data bank performs only one of write and read operations during a clock period.

Abstract: The data elements for a column of a table are fetched from irregular address locations in memory and stored as vector data with a regular address increment. Vector designating data is also generated which includes at least the first element address of the stored vector data and the increment of the vector. The vector data is processed by a program routine which can perform the processing required by a selected command and which includes vector instructions each designating at least one set of vector data elements to be executed, in such a manner that vector data elements are fetched successively from the data storage device and are supplied successively to a pipelined arithmetic or logical operation unit.

Abstract: Associative keys and retrieve outputs corresponding thereto are registered to an associative memory in a vector data conversion apparatus. Conversion vector data stored in the main storage and comprising vector elements of the same type of an associative key is sequentially read out for each vector element and is inputted to a comparator, which then compares the vector element with the associative keys beforehand registered to the associative memory so as to determine whether or not a matching condition exists therebetween. When the comparator detects the matching condition, a retrieve output corresponding to the matched associative key is read out from the associative memory and is stored in the main storage. While the conversion vector data is sequentially read out for each vector in this manner, the retrieve output data is sequentially stored in the main storage so as to generate the converted vector data comprising the retrieve output data as vector elements.

Abstract: A vector processor for sequentially reading out elements of a plurality of vector operands and sequentially storing the results of operations to the vector operands, comprising: operand counters for indicating the element numbers for every operand; address registers for every operand; a first comparator for comparing each element of the vector; maximum number registers for storing the maximum numbers of elements of the respective operands; a second comparator for comparing the operand counter of each operand with the content of the maximum number registers of each operand with respect to each operand; and a control circuit for independently updating the operand counters and operand address registers of ech operand in response to all of or parts of the outputs of the first and second comparators.

Abstract: An operation unit has a significant digit number judging circuit in which to detect as to whether or not a significant digit number of exponent part variable length data obtained as an arithmetic result becomes smaller than a specified minimum significant digit number, this operation unit manipulating data characterized in that exponent and mantissa parts thereof vary in length according to data values and its data length is fixed. In a first embodiment, there is a circuit for detecting the significant digit number of the resultant data with a variable length exponent part, the data being gained by a step wherein exponent and mantissa data are combined by using the exponent data of the resultant fixed length exponent and mantissa data.

Abstract: A vector processing system including a main storage for storing vector instructions and vector data, an instruction register for holding a vector instruction read out of the main storage, a decoder for decoding the vector instruction held in the instruction register, and an execution unit, operative to implement a vector operation in response to an output of the decoder, including a facility which, when a sort instruction inclusive of a vector starting address, increment switching parameter and an operation switching parameter has been set up in the instruction register, implements a sorting process specified by the instruction for vector data stored in the main storage, the facility including a circuit in which the operation switching parameter is set and which produces an operation switching signal in compliance with the number of operations and the position of a vector element to be operated, a circuit in which the increment switching parameter is set and which produces an increment switching signal in com

Abstract: A data processing system having a plurality of FIFO memories and a plurality of ALUs and in which a FIFO memory may be selected to receive a set of data signals from an ALU and at the same time to be selected to provide a set of data signals to another ALU, with the result that the selected FIFO memory performs read and write operations concurrently and intermittently. Also, a set of data signals held by one of the FIFO memories may be transferred to a selected ALU for effecting a logical or arithmetic operation thereon, and the data signals representing the result of the logical or arithmetic operation thereon, and the data signals representing the result of the logical or arithmetic operation by the selected ALU may be transferred to another FIFO memory.

Abstract: In order to allow fast execution of branch instructions even with the possibility of branching to different target instructions from the same branch instruction, a target instruction storage provides the target instruction in response to the branch instruction address and address data associated with a target instruction address.