Patents by Inventor Shunichi Yoshida

Shunichi Yoshida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220403571
    Abstract: A nonwoven fabric manufacturing facility includes a fiber assembly manufacturing step and a heating and drawing step. In the fiber assembly manufacturing step, fibers formed using an electrospinning method are collected to form a fiber assembly. In the heating and drawing step, the fiber assembly is drawn to form nonwoven fabric in a state where the fiber assembly is heated to a melting point of the fibers. In the formed nonwoven fabric, an average pore diameter is 15 ?m or more, a relative standard deviation of a pore diameter distribution is 0.1 or less, and an average fiber diameter of the fibers is 3 ?m or less.
    Type: Application
    Filed: August 24, 2022
    Publication date: December 22, 2022
    Applicant: FUJIFILM Corporation
    Inventors: Kenichi UMEMORI, Shunichi YOSHIDA
  • Publication number: 20070295426
    Abstract: A passivation film including a nitride-reformed layer that excludes chromium nitride (CrN) is formed on a surface of an austenitic stainless steel. The passivation film composed of chromium oxide functions as protection film against lead-free solder. As a result, the surface of stainless steel is hard to be corroded even when it contacts with the lead-free solder in its melted solder, thereby improving its corrosion resistance and its wear resistance substantially. In a case of SUS316 stainless steel, on an outermost surface of which the passivation film is formed, a period of lapsed time until corrosion of the stainless steel starts extends to about 500 hours as line Le shown in FIG. 4, and its corrosion depth indicates shallower one (20 through 25 ?m) as compared with the conventional one, thereby expecting that its durable year can be improved to an extent similar to that using a lead-filled solder, in order to obtain a stainless steel with enhanced corrosion resistance.
    Type: Application
    Filed: March 25, 2005
    Publication date: December 27, 2007
    Applicants: SONY CORPORATION, TAMURA CORPORATION, TAMURA FA SYSTEM CORPORATION, KYOKUTO NITRIDING CO., LTD.
    Inventors: Takashi Saito, Kaoru Mizumura, Teruo Okano, Kozo Kezuka, Masaki Iijima, Shunichi Yoshida
  • Publication number: 20020051016
    Abstract: A geometrical arithmetic unit obtains display coordinate data by coordinate transformation of drawing data, transfers the display coordinate data to the drawing unit when the drawing data is rotation target drawing data, and transfers the display coordinate data to a processor when the drawing data is non-rotation target drawing data. A processor controls transfer of an image of the non-rotation target drawing data to the drawing memory based on the display coordinate data. A drawing unit produces a rotated image based on the rotation target drawing data, and transfers the rotated image to the drawing memory based on the display coordinate data. Therefore, the processor and the drawing unit can perform the processing in parallel so that the drawing processing speed can be increased, and the drawing processing can be performed smoothly.
    Type: Application
    Filed: August 21, 2001
    Publication date: May 2, 2002
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shohei Moriwaki, Shunichi Yoshida, Kingo Wakimoto
  • Patent number: 5983023
    Abstract: A processor containing a cache memory having its storage capacity enlarged while suppressing area increases is provided. The processor includes an SRAM (Static Random Access Memory) cache memory and a DRAM (Dynamic RAM) cache memory of a large storage capacity. The SRAM cache memory and the DRAM cache memory are coupled to the processor through a processor bus. The SRAM cache memory and the DRAM cache memory transfer data through an internal transfer bus provided separately from the processor bus and having a larger width.
    Type: Grant
    Filed: July 2, 1997
    Date of Patent: November 9, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shohei Moriwaki, Shunichi Yoshida, Hideharu Toyomoto