Patents by Inventor Shunitsu KOHARA

Shunitsu KOHARA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200242842
    Abstract: [Problem] An information processing device, an information processing method, and a program are to be provided. [Solution] An information processing device including a display control unit that controls, when recognition information related to recognition based on sensing of a real object includes first recognition information, shielding display representing shielding of a virtual object by the real object such that the shielding display presents a first boundary representation at a boundary between the virtual object and the real object or at a position near the boundary, and controls, when the recognition information includes second recognition information different from the first recognition information, the shielding display such that the shielding display presents a second boundary representation different from the first boundary representation at the boundary or at a position near the boundary.
    Type: Application
    Filed: May 15, 2018
    Publication date: July 30, 2020
    Inventors: RYO FUKAZAWA, HIROTAKE ICHIKAWA, HIROYUKI AGA, ATSUSHI ISHIHARA, SHINICHI TAKEMURA, MIWA ICHIKAWA, SHUNITSU KOHARA, RYOSUKE MURATA, KENJI SUGIHARA, MARI SAITO
  • Patent number: 10649891
    Abstract: A storage device includes a nonvolatile memory, and a controller configured to perform, in response to commands from the host device, a read operation and a write operation on the nonvolatile memory. The controller divides a logical address space of the storage device into a plurality of subspaces and manages a priority value for each of the subspaces, the priority values of the subspaces determining an order for setting up the subspaces upon start-up of the storage device.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: May 12, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Satoshi Arai, Shunitsu Kohara, Kazuya Kitsunai, Yoshihisa Kojima, Hiroyuki Nemoto
  • Publication number: 20200143774
    Abstract: [Problem] To provide an information processing device, an information processing method, and a computer program. [Solution] To provide an information processing device including a display control unit that controls display so that, of a first real object and a second real object present in a real space that are recognized as candidates for an object to be operated, in a case in which the first real object is selected by a user as the object to be operated, a first virtual object corresponding to the first real object is displayed at a first position in the real space corresponding to a position of the first real object based on the selection made by the user, and in a case in which the second real object is selected by the user as the object to be operated, a second virtual object corresponding to the second real object is displayed at a second position in the real space corresponding to a position of the second real object based on the selection made by the user.
    Type: Application
    Filed: May 2, 2018
    Publication date: May 7, 2020
    Inventors: SHUNITSU KOHARA, RYO FUKAZAWA, KEI NITTA, KOICHI KAWASAKI, HIROTAKE ICHIKAWA
  • Patent number: 10372543
    Abstract: According to one embodiment, a memory system is connectable to a host. The memory system includes a nonvolatile first memory, a volatile second memory and a controller. The nonvolatile first memory stores translation information. The translation information associates a logical address and a physical address. The volatile second memory stores location information. The location information associates a logical address and a location where the translation information is stored in the first memory. The controller saves a first memory image in the first memory at a first timing, and saves a second memory image in the first memory at a second timing different from the first timing. The first memory image is a part of a memory image of the location information. The second memory image is another part, different form the first memory image, of the memory image of the location information.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: August 6, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kazuya Kitsunai, Shunitsu Kohara, Satoshi Arai, Yoshihisa Kojima
  • Patent number: 10095413
    Abstract: According to one embodiment, a memory system which is connectable to a host, the memory system includes a first memory as a nonvolatile memory storing information associated with an address translation between a logical address and a physical address, a second memory temporarily storing a part of the information at least, a first controller executing a read operation and a write operation of the information for the second memory in a first data unit, the first data unit being changeable and being a data size of one of regions obtained by dividing in a first address space, the part of the information at least stored in the first memory, and a second controller executing a read operation and a write operation of the information for the first memory in a second data unit different from the first data unit.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: October 9, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shunitsu Kohara, Kazuya Kitsunai, Satoshi Arai, Yoshihisa Kojima
  • Patent number: 9940071
    Abstract: A memory system includes a non-volatile memory and a controller circuit. The controller circuit is configured to carry out an atomic write operation in the non-volatile memory in response to an atomic write command, and selectively carry out one of a first operation and a second operation corresponding to address mapping between a logical address and a physical address of the non-volatile memory, along with the atomic write operation. When the first operation is selected, the controller circuit starts to update the address mapping after receiving a notification that writing of all data of the atomic write operation has been completed. When the second operation is carried out, the controller circuit starts to update the address mapping before receiving the notification.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: April 10, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Hiroyuki Nemoto, Shunitsu Kohara, Kazuya Kitsunai, Satoshi Arai
  • Publication number: 20180060228
    Abstract: A storage device includes a nonvolatile memory, and a controller configured to perform, in response to commands from the host device, a read operation and a write operation on the nonvolatile memory. The controller divides a logical address space of the storage device into a plurality of subspaces and manages a priority value for each of the subspaces, the priority values of the subspaces determining an order for setting up the subspaces upon start-up of the storage device.
    Type: Application
    Filed: August 24, 2017
    Publication date: March 1, 2018
    Inventors: Satoshi ARAI, Shunitsu KOHARA, Kazuya KITSUNAI, Yoshihisa KOJIMA, Hiroyuki NEMOTO
  • Publication number: 20170255564
    Abstract: According to one embodiment, a memory system is connectable to a host. The memory system includes a nonvolatile first memory, a volatile second memory and a controller. The nonvolatile first memory stores translation information. The translation information associates a logical address and a physical address. The volatile second memory stores location information. The location information associates a logical address and a location where the translation information is stored in the first memory. The controller saves a first memory image in the first memory at a first timing, and saves a second memory image in the first memory at a second timing different from the first timing. The first memory image is a part of a memory image of the location information. The second memory image is another part, different form the first memory image, of the memory image of the location information.
    Type: Application
    Filed: September 12, 2016
    Publication date: September 7, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kazuya KITSUNAI, Shunitsu KOHARA, Satoshi ARAI, Yoshihisa KOJIMA
  • Publication number: 20170220253
    Abstract: According to one embodiment, a memory system which is connectable to a host, the memory system includes a first memory as a nonvolatile memory storing information associated with an address translation between a logical address and a physical address, a second memory temporarily storing a part of the information at least, a first controller executing a read operation and a write operation of the information for the second memory in a first data unit, the first data unit being changeable and being a data size of one of regions obtained by dividing in a first address space, the part of the information at least stored in the first memory, and a second controller executing a read operation and a write operation of the information for the first memory in a second data unit different from the first data unit.
    Type: Application
    Filed: July 13, 2016
    Publication date: August 3, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shunitsu KOHARA, Kazuya KITSUNAI, Satoshi ARAI, Yoshihisa KOJIMA
  • Publication number: 20170199687
    Abstract: According to one embodiment, a memory system includes a nonvolatile first memory, a second memory, and a processor. The second memory includes a first cache area for caching in units of a data-unit. The processor transfers the first data and translation information for the first data into the first memory and performs garbage collection. The garbage collection includes first to third process. The first process is determining whether second data is valid or invalid on the basis of translation information for the second data. The second data is corresponding to the first data in the first memory. The second process is copying third data within the first memory. The third data is corresponding to the second data determined to be valid. The third process is updating translation information for the third data. The processor caches, in the first cache area, only a data-unit including translation information for the first process.
    Type: Application
    Filed: September 2, 2016
    Publication date: July 13, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shunitsu KOHARA, Kazuya KITSUNAI, Satoshi ARAI, Yoshihisa KOJIMA
  • Publication number: 20170160988
    Abstract: A memory system includes a non-volatile memory and a controller circuit. The controller circuit is configured to carry out an atomic write operation in the non-volatile memory in response to an atomic write command, and selectively carry out one of a first operation and a second operation corresponding to address mapping between a logical address and a physical address of the non-volatile memory, along with the atomic write operation. When the first operation is selected, the controller circuit starts to update the address mapping after receiving a notification that writing of all data of the atomic write operation has been completed. When the second operation is carried out, the controller circuit starts to update the address mapping before receiving the notification.
    Type: Application
    Filed: August 22, 2016
    Publication date: June 8, 2017
    Inventors: Hiroyuki NEMOTO, Shunitsu KOHARA, Kazuya KITSUNAI, Satoshi ARAI
  • Publication number: 20170031601
    Abstract: According to one embodiment, a memory system is connectable to a host. The memory system includes a first memory including a cache area, and a memory controller. The memory controller sets the available amount of the cache area in response to a first command from the host. In a case where the available amount of the cache area is successfully set, the memory controller transmits a setting completion notification to the host. In a case where the available amount of the cache area cannot be set, the memory controller transmits a notification of non-settable to the host.
    Type: Application
    Filed: March 11, 2016
    Publication date: February 2, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Satoshi ARAI, Kazuya KITSUNAI, Shunitsu KOHARA, Hiroyuki NEMOTO