Patents by Inventor Shunitsu KOHARA

Shunitsu KOHARA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230127539
    Abstract: An information processing apparatus (1) according to an aspect of an embodiment includes a drawing unit (6b), a setting unit (6c), and an expansion unit (6e). The drawing unit (6b) draws a virtual object displayed on a display device (4). The setting unit (6c) sets a shielding object indicating the shape of a real object existing in a real space and to be superimposed on the real object. The expansion unit (6e) expands the shielding object toward the virtual object side when a shielding condition indicating that the virtual object drawn by the drawing unit (6b) is partially shielded by the shielding object set by the setting unit is satisfied.
    Type: Application
    Filed: March 29, 2021
    Publication date: April 27, 2023
    Inventors: HARUKA FUJISAWA, SHUNITSU KOHARA, HAJIME WAKABAYASHI, MAKOTO DANIEL TOKUNAGA
  • Publication number: 20230132045
    Abstract: Provided is an information processing device, an information processing method, and a recording medium capable of suppressing a decrease in visibility of a display image in a case where a user's line of sight moves at a high speed. An information processing device (1) according to the present disclosure includes a resolution control unit (14). The resolution control unit (14) sets a high-resolution region including a gaze point of a user and a low-resolution region not including the gaze point of the user to a display image displayed by a display device and temporarily expands the high-resolution region toward a virtual object in a case where the virtual object enters the high-resolution region.
    Type: Application
    Filed: February 26, 2021
    Publication date: April 27, 2023
    Inventors: FUJIO ARAI, KAZUNORI ASAYAMA, GEN HAMADA, YU NAKADA, SHUNITSU KOHARA, HAJIME WAKABAYASHI
  • Publication number: 20230120092
    Abstract: An information processing device includes an output control unit (173) that controls output on a presentation device so as to present content associated with an absolute position in a real space, to a first user, a determination unit (171) that determines a self-position in the real space, a transmission unit (172) that transmits a signal requesting rescue to a device positioned in the real space, when reliability of determination by the determination unit (171) is reduced, an acquisition unit (174) that acquires information about the self-position estimated from an image including the first user captured by the device according to the signal; and a correction unit (175) that corrects the self-position based on the information about the self-position acquired by the acquisition unit (174).
    Type: Application
    Filed: February 4, 2021
    Publication date: April 20, 2023
    Inventors: DAITA KOBAYASHI, HAJIME WAKABAYASHI, HIROTAKE ICHIKAWA, ATSUSHI ISHIHARA, HIDENORI AOKI, YOSHINORI OGAKI, YU NAKADA, RYOSUKE MURATA, TOMOHIKO GOTOH, SHUNITSU KOHARA, HARUKA FUJISAWA, MAKOTO DANIEL TOKUNAGA
  • Publication number: 20220414945
    Abstract: A device and a method for performing AR image display control in which flicker in a boundary region between a virtual object and a real object is not noticeable are provided.
    Type: Application
    Filed: October 28, 2020
    Publication date: December 29, 2022
    Inventors: SHUNITSU KOHARA, HIDENORI AOKI, HIROTAKE ICHIKAWA, SHINTARO TSUTSUI, HIROSHI MATSUYAMA, HAJIME WAKABAYASHI, ATSUSHI ISHIHARA
  • Patent number: 11288869
    Abstract: An information processing device including a display control unit that controls, when recognition information related to recognition based on sensing of a real object includes first recognition information, shielding display representing shielding of a virtual object by the real object such that the shielding display presents a first boundary representation at a boundary between the virtual object and the real object or at a position near the boundary, and controls, when the recognition information includes second recognition information different from the first recognition information, the shielding display such that the shielding display presents a second boundary representation different from the first boundary representation at the boundary or at a position near the boundary.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: March 29, 2022
    Assignee: SONY CORPORATION
    Inventors: Ryo Fukazawa, Hirotake Ichikawa, Hiroyuki Aga, Atsushi Ishihara, Shinichi Takemura, Miwa Ichikawa, Shunitsu Kohara, Ryosuke Murata, Kenji Sugihara, Mari Saito
  • Publication number: 20210377515
    Abstract: An information processing device including: an acquisition unit that acquires information according to a recognition result of the position and posture of a viewpoint; a projection processing unit that projects a target object on the basis of the position and posture of a first viewpoint onto a first projection surface defined in association with the first viewpoint, and associates second information according to the relative position and posture relationship between the first viewpoint and the object with first information according to a result of the projection; a correction processing unit that restores three-dimensional information of the object on the basis of the first information and the second information, and reprojects the object according to the relative position and posture relationship between the restored object and a second viewpoint onto a second projection surface defined in association with the second viewpoint; and an output control unit that causes an output unit to present display informa
    Type: Application
    Filed: September 30, 2019
    Publication date: December 2, 2021
    Applicant: SONY GROUP CORPORATION
    Inventors: Hiroyuki AGA, Atsushi ISHIHARA, Mitsuru NISHIBE, Koichi KAWASAKI, Hirotake ICHIKAWA, Hajime WAKABAYASHI, Shunitsu KOHARA, Ryosuke MURATA
  • Publication number: 20200242842
    Abstract: [Problem] An information processing device, an information processing method, and a program are to be provided. [Solution] An information processing device including a display control unit that controls, when recognition information related to recognition based on sensing of a real object includes first recognition information, shielding display representing shielding of a virtual object by the real object such that the shielding display presents a first boundary representation at a boundary between the virtual object and the real object or at a position near the boundary, and controls, when the recognition information includes second recognition information different from the first recognition information, the shielding display such that the shielding display presents a second boundary representation different from the first boundary representation at the boundary or at a position near the boundary.
    Type: Application
    Filed: May 15, 2018
    Publication date: July 30, 2020
    Inventors: RYO FUKAZAWA, HIROTAKE ICHIKAWA, HIROYUKI AGA, ATSUSHI ISHIHARA, SHINICHI TAKEMURA, MIWA ICHIKAWA, SHUNITSU KOHARA, RYOSUKE MURATA, KENJI SUGIHARA, MARI SAITO
  • Patent number: 10649891
    Abstract: A storage device includes a nonvolatile memory, and a controller configured to perform, in response to commands from the host device, a read operation and a write operation on the nonvolatile memory. The controller divides a logical address space of the storage device into a plurality of subspaces and manages a priority value for each of the subspaces, the priority values of the subspaces determining an order for setting up the subspaces upon start-up of the storage device.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: May 12, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Satoshi Arai, Shunitsu Kohara, Kazuya Kitsunai, Yoshihisa Kojima, Hiroyuki Nemoto
  • Publication number: 20200143774
    Abstract: [Problem] To provide an information processing device, an information processing method, and a computer program. [Solution] To provide an information processing device including a display control unit that controls display so that, of a first real object and a second real object present in a real space that are recognized as candidates for an object to be operated, in a case in which the first real object is selected by a user as the object to be operated, a first virtual object corresponding to the first real object is displayed at a first position in the real space corresponding to a position of the first real object based on the selection made by the user, and in a case in which the second real object is selected by the user as the object to be operated, a second virtual object corresponding to the second real object is displayed at a second position in the real space corresponding to a position of the second real object based on the selection made by the user.
    Type: Application
    Filed: May 2, 2018
    Publication date: May 7, 2020
    Inventors: SHUNITSU KOHARA, RYO FUKAZAWA, KEI NITTA, KOICHI KAWASAKI, HIROTAKE ICHIKAWA
  • Patent number: 10372543
    Abstract: According to one embodiment, a memory system is connectable to a host. The memory system includes a nonvolatile first memory, a volatile second memory and a controller. The nonvolatile first memory stores translation information. The translation information associates a logical address and a physical address. The volatile second memory stores location information. The location information associates a logical address and a location where the translation information is stored in the first memory. The controller saves a first memory image in the first memory at a first timing, and saves a second memory image in the first memory at a second timing different from the first timing. The first memory image is a part of a memory image of the location information. The second memory image is another part, different form the first memory image, of the memory image of the location information.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: August 6, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kazuya Kitsunai, Shunitsu Kohara, Satoshi Arai, Yoshihisa Kojima
  • Patent number: 10095413
    Abstract: According to one embodiment, a memory system which is connectable to a host, the memory system includes a first memory as a nonvolatile memory storing information associated with an address translation between a logical address and a physical address, a second memory temporarily storing a part of the information at least, a first controller executing a read operation and a write operation of the information for the second memory in a first data unit, the first data unit being changeable and being a data size of one of regions obtained by dividing in a first address space, the part of the information at least stored in the first memory, and a second controller executing a read operation and a write operation of the information for the first memory in a second data unit different from the first data unit.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: October 9, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shunitsu Kohara, Kazuya Kitsunai, Satoshi Arai, Yoshihisa Kojima
  • Patent number: 9940071
    Abstract: A memory system includes a non-volatile memory and a controller circuit. The controller circuit is configured to carry out an atomic write operation in the non-volatile memory in response to an atomic write command, and selectively carry out one of a first operation and a second operation corresponding to address mapping between a logical address and a physical address of the non-volatile memory, along with the atomic write operation. When the first operation is selected, the controller circuit starts to update the address mapping after receiving a notification that writing of all data of the atomic write operation has been completed. When the second operation is carried out, the controller circuit starts to update the address mapping before receiving the notification.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: April 10, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Hiroyuki Nemoto, Shunitsu Kohara, Kazuya Kitsunai, Satoshi Arai
  • Publication number: 20180060228
    Abstract: A storage device includes a nonvolatile memory, and a controller configured to perform, in response to commands from the host device, a read operation and a write operation on the nonvolatile memory. The controller divides a logical address space of the storage device into a plurality of subspaces and manages a priority value for each of the subspaces, the priority values of the subspaces determining an order for setting up the subspaces upon start-up of the storage device.
    Type: Application
    Filed: August 24, 2017
    Publication date: March 1, 2018
    Inventors: Satoshi ARAI, Shunitsu KOHARA, Kazuya KITSUNAI, Yoshihisa KOJIMA, Hiroyuki NEMOTO
  • Publication number: 20170255564
    Abstract: According to one embodiment, a memory system is connectable to a host. The memory system includes a nonvolatile first memory, a volatile second memory and a controller. The nonvolatile first memory stores translation information. The translation information associates a logical address and a physical address. The volatile second memory stores location information. The location information associates a logical address and a location where the translation information is stored in the first memory. The controller saves a first memory image in the first memory at a first timing, and saves a second memory image in the first memory at a second timing different from the first timing. The first memory image is a part of a memory image of the location information. The second memory image is another part, different form the first memory image, of the memory image of the location information.
    Type: Application
    Filed: September 12, 2016
    Publication date: September 7, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kazuya KITSUNAI, Shunitsu KOHARA, Satoshi ARAI, Yoshihisa KOJIMA
  • Publication number: 20170220253
    Abstract: According to one embodiment, a memory system which is connectable to a host, the memory system includes a first memory as a nonvolatile memory storing information associated with an address translation between a logical address and a physical address, a second memory temporarily storing a part of the information at least, a first controller executing a read operation and a write operation of the information for the second memory in a first data unit, the first data unit being changeable and being a data size of one of regions obtained by dividing in a first address space, the part of the information at least stored in the first memory, and a second controller executing a read operation and a write operation of the information for the first memory in a second data unit different from the first data unit.
    Type: Application
    Filed: July 13, 2016
    Publication date: August 3, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shunitsu KOHARA, Kazuya KITSUNAI, Satoshi ARAI, Yoshihisa KOJIMA
  • Publication number: 20170199687
    Abstract: According to one embodiment, a memory system includes a nonvolatile first memory, a second memory, and a processor. The second memory includes a first cache area for caching in units of a data-unit. The processor transfers the first data and translation information for the first data into the first memory and performs garbage collection. The garbage collection includes first to third process. The first process is determining whether second data is valid or invalid on the basis of translation information for the second data. The second data is corresponding to the first data in the first memory. The second process is copying third data within the first memory. The third data is corresponding to the second data determined to be valid. The third process is updating translation information for the third data. The processor caches, in the first cache area, only a data-unit including translation information for the first process.
    Type: Application
    Filed: September 2, 2016
    Publication date: July 13, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shunitsu KOHARA, Kazuya KITSUNAI, Satoshi ARAI, Yoshihisa KOJIMA
  • Publication number: 20170160988
    Abstract: A memory system includes a non-volatile memory and a controller circuit. The controller circuit is configured to carry out an atomic write operation in the non-volatile memory in response to an atomic write command, and selectively carry out one of a first operation and a second operation corresponding to address mapping between a logical address and a physical address of the non-volatile memory, along with the atomic write operation. When the first operation is selected, the controller circuit starts to update the address mapping after receiving a notification that writing of all data of the atomic write operation has been completed. When the second operation is carried out, the controller circuit starts to update the address mapping before receiving the notification.
    Type: Application
    Filed: August 22, 2016
    Publication date: June 8, 2017
    Inventors: Hiroyuki NEMOTO, Shunitsu KOHARA, Kazuya KITSUNAI, Satoshi ARAI
  • Publication number: 20170031601
    Abstract: According to one embodiment, a memory system is connectable to a host. The memory system includes a first memory including a cache area, and a memory controller. The memory controller sets the available amount of the cache area in response to a first command from the host. In a case where the available amount of the cache area is successfully set, the memory controller transmits a setting completion notification to the host. In a case where the available amount of the cache area cannot be set, the memory controller transmits a notification of non-settable to the host.
    Type: Application
    Filed: March 11, 2016
    Publication date: February 2, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Satoshi ARAI, Kazuya KITSUNAI, Shunitsu KOHARA, Hiroyuki NEMOTO